diff mbox series

[RESEND] memory: jz4780_nemc: Only request IO memory the driver will use

Message ID 20200723090414.5824-1-paul@crapouillou.net (mailing list archive)
State Not Applicable
Headers show
Series [RESEND] memory: jz4780_nemc: Only request IO memory the driver will use | expand

Commit Message

Paul Cercueil July 23, 2020, 9:04 a.m. UTC
The driver only uses the registers up to offset 0x54. Since the EFUSE
registers are in the middle of the NEMC registers, we only request
the registers we will use for now - that way the EFUSE driver can
probe too.

Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    Thomas:
    
    drivers/memory/ has no dedicated maintainer, so sending this
    patch upstream is like sending a bottle to the sea. Since it
    touches a driver for a Ingenic SoC, if Greg doesn't take it
    (I don't blame him - he's a busy man), could you take it in
    your tree?
    
    Thanks,
    -Paul

 drivers/memory/jz4780-nemc.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Comments

Paul Cercueil July 25, 2020, 12:40 p.m. UTC | #1
Thomas, Greg,

Nevermind the previous note, it turns out a new maintainer (Krzysztof) 
just appeared for drivers/memory/, I will upstream this patch through 
him.

Cheers,
-Paul


Le jeu. 23 juil. 2020 à 11:04, Paul Cercueil <paul@crapouillou.net> a 
écrit :
> The driver only uses the registers up to offset 0x54. Since the EFUSE
> registers are in the middle of the NEMC registers, we only request
> the registers we will use for now - that way the EFUSE driver can
> probe too.
> 
> Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> 
> Notes:
>     Thomas:
> 
>     drivers/memory/ has no dedicated maintainer, so sending this
>     patch upstream is like sending a bottle to the sea. Since it
>     touches a driver for a Ingenic SoC, if Greg doesn't take it
>     (I don't blame him - he's a busy man), could you take it in
>     your tree?
> 
>     Thanks,
>     -Paul
> 
>  drivers/memory/jz4780-nemc.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/memory/jz4780-nemc.c 
> b/drivers/memory/jz4780-nemc.c
> index b232ed279fc3..647267ea8c63 100644
> --- a/drivers/memory/jz4780-nemc.c
> +++ b/drivers/memory/jz4780-nemc.c
> @@ -8,6 +8,7 @@
> 
>  #include <linux/clk.h>
>  #include <linux/init.h>
> +#include <linux/io.h>
>  #include <linux/math64.h>
>  #include <linux/of.h>
>  #include <linux/of_address.h>
> @@ -288,7 +289,19 @@ static int jz4780_nemc_probe(struct 
> platform_device *pdev)
>  	nemc->dev = dev;
> 
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	nemc->base = devm_ioremap_resource(dev, res);
> +
> +	/*
> +	 * The driver only uses the registers up to offset 0x54. Since the 
> EFUSE
> +	 * registers are in the middle of the NEMC registers, we only 
> request
> +	 * the registers we will use for now - that way the EFUSE driver can
> +	 * probe too.
> +	 */
> +	if (!devm_request_mem_region(dev, res->start, 0x54, dev_name(dev))) 
> {
> +		dev_err(dev, "unable to request I/O memory region\n");
> +		return -EBUSY;
> +	}
> +
> +	nemc->base = devm_ioremap(dev, res->start, resource_size(res));
>  	if (IS_ERR(nemc->base)) {
>  		dev_err(dev, "failed to get I/O memory\n");
>  		return PTR_ERR(nemc->base);
> --
> 2.27.0
>
diff mbox series

Patch

diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c
index b232ed279fc3..647267ea8c63 100644
--- a/drivers/memory/jz4780-nemc.c
+++ b/drivers/memory/jz4780-nemc.c
@@ -8,6 +8,7 @@ 
 
 #include <linux/clk.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/math64.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -288,7 +289,19 @@  static int jz4780_nemc_probe(struct platform_device *pdev)
 	nemc->dev = dev;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	nemc->base = devm_ioremap_resource(dev, res);
+
+	/*
+	 * The driver only uses the registers up to offset 0x54. Since the EFUSE
+	 * registers are in the middle of the NEMC registers, we only request
+	 * the registers we will use for now - that way the EFUSE driver can
+	 * probe too.
+	 */
+	if (!devm_request_mem_region(dev, res->start, 0x54, dev_name(dev))) {
+		dev_err(dev, "unable to request I/O memory region\n");
+		return -EBUSY;
+	}
+
+	nemc->base = devm_ioremap(dev, res->start, resource_size(res));
 	if (IS_ERR(nemc->base)) {
 		dev_err(dev, "failed to get I/O memory\n");
 		return PTR_ERR(nemc->base);