diff mbox series

MIPS: fix missing MSACSR and upper MSA initialization for cc97ab23

Message ID 20200831020145.31706-2-huangpei@loongson.cn (mailing list archive)
State Superseded
Headers show
Series MIPS: fix missing MSACSR and upper MSA initialization for cc97ab23 | expand

Commit Message

Huang Pei Aug. 31, 2020, 2:01 a.m. UTC
In cc97ab235f3fe32401ca198cebe6f42642e95770, init_fp_ctx just initialize the
fp/msa context, and own_fp_inatomic just restore FCSR and 64bit FP regs from
it, but miss MSACSR and upper MSA regs for MSA, so MSACSR and MSA upper regs's
value from previous task on current cpu can leak into current task and cause
unpredictable behavior when MSA context not initialized.

Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
 arch/mips/kernel/traps.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Thomas Bogendoerfer Aug. 31, 2020, 9:07 p.m. UTC | #1
On Mon, Aug 31, 2020 at 10:01:45AM +0800, Huang Pei wrote:
> In cc97ab235f3fe32401ca198cebe6f42642e95770, init_fp_ctx just initialize the

checkpatch will warn you about this:

WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7: 
In cc97ab235f3fe32401ca198cebe6f42642e95770, init_fp_ctx just initialize the

Use cc97ab235f3f ("MIPS: Simplify FP context initialization") instead of
the pure hash.


> fp/msa context, and own_fp_inatomic just restore FCSR and 64bit FP regs from
> it, but miss MSACSR and upper MSA regs for MSA, so MSACSR and MSA upper regs's
> value from previous task on current cpu can leak into current task and cause
> unpredictable behavior when MSA context not initialized.

And add

Fixes: cc97ab235f3f ("MIPS: Simplify FP context initialization")

before your Signed-off-by, which is what I meant with "add fixes tag".

> 
> Signed-off-by: Huang Pei <huangpei@loongson.cn>
> ---
>  arch/mips/kernel/traps.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
Huang Pei Sept. 1, 2020, 7:13 a.m. UTC | #2
On Mon, Aug 31, 2020 at 11:07:33PM +0200, Thomas Bogendoerfer wrote:
> On Mon, Aug 31, 2020 at 10:01:45AM +0800, Huang Pei wrote:
> > In cc97ab235f3fe32401ca198cebe6f42642e95770, init_fp_ctx just initialize the
> 
> checkpatch will warn you about this:
> 
> WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line)
> #7: 
> In cc97ab235f3fe32401ca198cebe6f42642e95770, init_fp_ctx just initialize the
> 
> Use cc97ab235f3f ("MIPS: Simplify FP context initialization") instead of
> the pure hash.
> 
> 
> > fp/msa context, and own_fp_inatomic just restore FCSR and 64bit FP regs from
> > it, but miss MSACSR and upper MSA regs for MSA, so MSACSR and MSA upper regs's
> > value from previous task on current cpu can leak into current task and cause
> > unpredictable behavior when MSA context not initialized.
> 
> And add
> 
> Fixes: cc97ab235f3f ("MIPS: Simplify FP context initialization")
> 
> before your Signed-off-by, which is what I meant with "add fixes tag".
> 
> > 
> > Signed-off-by: Huang Pei <huangpei@loongson.cn>
> > ---
> >  arch/mips/kernel/traps.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> 
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

Thank you for your time, I will reread submitting-patches.rst and
recheck all my patches
diff mbox series

Patch

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 38aa07ccdbcc..cf788591f091 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1287,6 +1287,18 @@  static int enable_restore_fp_context(int msa)
 		err = own_fpu_inatomic(1);
 		if (msa && !err) {
 			enable_msa();
+			/*
+			 * with MSA enabled, userspace can see MSACSR
+			 * and MSA regs, but the values in them are from
+			 * other task before current task, restore them
+			 * from saved fp/msa context
+			 */
+			write_msa_csr(current->thread.fpu.msacsr);
+			/*
+			 * own_fpu_inatomic(1) just restore low 64bit,
+			 * fix the high 64bit
+			 */
+			init_msa_upper();
 			set_thread_flag(TIF_USEDMSA);
 			set_thread_flag(TIF_MSA_CTX_LIVE);
 		}