diff mbox series

[v2,2/2] MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.

Message ID 20200921174522.33866-3-zhouyanjie@wanyeetech.com (mailing list archive)
State Superseded
Headers show
Series [v2,1/2] MIPS: Ingenic: Add system type for new Ingenic SoCs. | expand

Commit Message

Zhou Yanjie Sept. 21, 2020, 5:45 p.m. UTC 
1.Fix bugs when detecting ways value of JZ4775's L2 cache.
2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    v1->v2:
    1.Add corrections to JZ4775's L2 cache ways parameter.
    2.Add Paul Cercueil's Reviewed-by.

 arch/mips/mm/sc-mips.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 97dc0511e63f..dd0a5becaabd 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -228,6 +228,7 @@  static inline int __init mips_sc_probe(void)
 		 * contradicted by all documentation.
 		 */
 		case MACH_INGENIC_JZ4770:
+		case MACH_INGENIC_JZ4775:
 			c->scache.ways = 4;
 			break;
 
@@ -236,6 +237,7 @@  static inline int __init mips_sc_probe(void)
 		 * but that is contradicted by all documentation.
 		 */
 		case MACH_INGENIC_X1000:
+		case MACH_INGENIC_X1000E:
 			c->scache.sets = 256;
 			c->scache.ways = 4;
 			break;