Message ID | 20200922012444.44089-2-zhouyanjie@wanyeetech.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 2372b506115b411c6127c94798d575e0cf5b58b6 |
Headers | show |
Series | Repair Ingenic SoCs L2 cache capacity detection. | expand |
diff --git a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml index 83c86cbe4716..dc21b4630c25 100644 --- a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml +++ b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml @@ -47,4 +47,9 @@ properties: items: - const: yna,cu1830-neo - const: ingenic,x1830 + + - description: YSH & ATIL General Board, CU2000 Module with Neo Backplane + items: + - const: yna,cu2000-neo + - const: ingenic,x2000e ...
Add bindings for Ingenic X2000E based board, prepare for later dts. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- Notes: v3: New patch. Documentation/devicetree/bindings/mips/ingenic/devices.yaml | 5 +++++ 1 file changed, 5 insertions(+)