From patchwork Fri Nov 13 09:10:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11902763 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FFD514C0 for ; Fri, 13 Nov 2020 09:11:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A4BB22226 for ; Fri, 13 Nov 2020 09:11:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VLSnDgif" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726338AbgKMJLE (ORCPT ); Fri, 13 Nov 2020 04:11:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726297AbgKMJK4 (ORCPT ); Fri, 13 Nov 2020 04:10:56 -0500 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0845FC0613D6; Fri, 13 Nov 2020 01:10:56 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id d142so7424802wmd.4; Fri, 13 Nov 2020 01:10:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+6p+tTyzAWgS+0TeiLAeHpt5VdrmCp8DE+ysIaEsgQc=; b=VLSnDgifad/Oyw9GBJjXEnHuIhvXXSp6y2mJNZr7gD9vzrsHWok8Gw6BwFaxriqV2h IH8NBThxwz8L5FpYFt1pEYKoa+yCWoD5JqH9vm6RaDcWK7O+1VnAl/9gL/Yhw2F0/LJX 7UhbcNGDgc7K38dIjmW1rZSTpgzbpj5xgseKaSeRCir6Ssa9B1veHsjPwGCm6y+IiLpw wcPGONfLu9jUDKzIPraKp2ai87NkLCvuph1Png0agS5uuuSlNM15xOWKUv2A15wEwhfa eZ8V8+9DOpbAhfz4RQ9KZu+uO4X7VNsiRcntZV1PpYv9czdiszu/chJqkhyRMItE6Tps jnGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+6p+tTyzAWgS+0TeiLAeHpt5VdrmCp8DE+ysIaEsgQc=; b=R7IOGIOTTkWUW5JppZ3M7AuPkXMHMuJ3LRpACAZbCaEeQYgcoqQrqzID+KNWNCuvRV oVuwHZPkLE1jkbLNHseMNOx90JEkPc9enU+gT14yoDP8TYdzBhTRGT3dbSLaQDxxwi1y ZX/A8xeDPpAbTK2RonKWwAC91qD/Lfvo4ZD2W/ZxLfANXzeNXO/5h47pSKxn5Eq9yo6R nUTu3N/J6mHUDwfv5l5kNu4TbF+2Im0cWIGUG9GIkKOGooP2lfq5FJ94Wf+TaY/jJCxi jADSc3GHhKFLDlvthfw+ZfHVIlBHkQIdjPlARFYErGlFiyXNXZR3QkCTkqZmC5AWm6K3 56Hg== X-Gm-Message-State: AOAM530cLJugVAR6wfrzKaEHC46KzBIlI3w7sdeWLVSfK/cN2YOl8GWC 3z/MPUGC1cn8j6WEfYXQLcg= X-Google-Smtp-Source: ABdhPJzT0Z/RfVMCQWFwvcU8xYLkXxVSc2/b4ArlKALH2h8mOEyNGwIQK6v6asvyycsMy5TEWKmeUQ== X-Received: by 2002:a1c:5a06:: with SMTP id o6mr1480204wmb.181.1605258654745; Fri, 13 Nov 2020 01:10:54 -0800 (PST) Received: from localhost.localdomain (245.red-79-158-78.dynamicip.rima-tde.net. [79.158.78.245]) by smtp.gmail.com with ESMTPSA id 15sm9266183wmg.1.2020.11.13.01.10.53 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Nov 2020 01:10:54 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name Subject: [PATCH v2 4/5] staging: mt7621-dts: make use of new 'mt7621-clk' Date: Fri, 13 Nov 2020 10:10:45 +0100 Message-Id: <20201113091046.30964-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201113091046.30964-1-sergio.paracuellos@gmail.com> References: <20201113091046.30964-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/gbpc1.dts | 11 ---- drivers/staging/mt7621-dts/mt7621.dtsi | 72 ++++++++++++-------------- 2 files changed, 33 insertions(+), 50 deletions(-) diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts index a7c0d3115d72..7716d0efe524 100644 --- a/drivers/staging/mt7621-dts/gbpc1.dts +++ b/drivers/staging/mt7621-dts/gbpc1.dts @@ -100,17 +100,6 @@ partition@50000 { }; }; -&sysclock { - compatible = "fixed-clock"; - /* This is normally 1/4 of cpuclock */ - clock-frequency = <225000000>; -}; - -&cpuclock { - compatible = "fixed-clock"; - clock-frequency = <900000000>; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 82aa93634eda..f64e66de4bf7 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -1,5 +1,6 @@ #include #include +#include / { #address-cells = <1>; @@ -27,26 +28,13 @@ aliases { serial0 = &uartlite; }; - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - - sysclock: sysclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* This is normally 1/4 of cpuclock */ - clock-frequency = <220000000>; - }; - - mmc_clock: mmc_clock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; + pll: pll { + compatible = "mediatek,mt7621-clk"; + ralink,sysctl = <&sysc>; + #clock-cells = <1>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "225m", "250m"; }; mmc_fixed_3v3: fixedregulator@0 { @@ -76,7 +64,7 @@ palmbus: palmbus@1E000000 { #size-cells = <1>; sysc: sysc@0 { - compatible = "mtk,mt7621-sysc"; + compatible = "mtk,mt7621-sysc", "syscon"; reg = <0x0 0x100>; }; @@ -100,8 +88,8 @@ i2c: i2c@900 { compatible = "mediatek,mt7621-i2c"; reg = <0x900 0x100>; - clocks = <&sysclock>; - + clocks = <&pll MT7621_CLK_I2C>; + clock-names = "i2c"; resets = <&rstctrl 16>; reset-names = "i2c"; @@ -118,8 +106,8 @@ i2s: i2s@a00 { compatible = "mediatek,mt7621-i2s"; reg = <0xa00 0x100>; - clocks = <&sysclock>; - + clocks = <&pll MT7621_CLK_I2S>; + clock-names = "i2s"; resets = <&rstctrl 17>; reset-names = "i2s"; @@ -155,8 +143,8 @@ uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; - clock-frequency = <50000000>; + clocks = <&pll MT7621_CLK_UART1>; + clock-names = "uart1"; interrupt-parent = <&gic>; interrupts = ; @@ -172,7 +160,7 @@ spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_SPI>; resets = <&rstctrl 18>; reset-names = "spi"; @@ -188,6 +176,8 @@ gdma: gdma@2800 { compatible = "ralink,rt3883-gdma"; reg = <0x2800 0x800>; + clocks = <&pll MT7621_CLK_GDMA>; + clock-names = "gdma"; resets = <&rstctrl 14>; reset-names = "dma"; @@ -205,6 +195,8 @@ hsdma: hsdma@7000 { compatible = "mediatek,mt7621-hsdma"; reg = <0x7000 0x1000>; + clocks = <&pll MT7621_CLK_HSDMA>; + clock-names = "hsdma"; resets = <&rstctrl 5>; reset-names = "hsdma"; @@ -315,11 +307,6 @@ rstctrl: rstctrl { #reset-cells = <1>; }; - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - sdhci: sdhci@1E130000 { status = "disabled"; @@ -338,7 +325,8 @@ sdhci: sdhci@1E130000 { pinctrl-0 = <&sdhci_pins>; pinctrl-1 = <&sdhci_pins>; - clocks = <&mmc_clock &mmc_clock>; + clocks = <&pll MT7621_CLK_SHXC>, + <&pll MT7621_CLK_50M>; clock-names = "source", "hclk"; interrupt-parent = <&gic>; @@ -353,7 +341,7 @@ xhci: xhci@1E1C0000 { 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_XTAL>; clock-names = "sys_ck"; interrupt-parent = <&gic>; @@ -372,7 +360,7 @@ gic: interrupt-controller@1fbc0000 { timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; @@ -385,6 +373,9 @@ nand: nand@1e003000 { 0x1e003800 0x800>; #address-cells = <1>; #size-cells = <1>; + + clocks = <&pll MT7621_CLK_NAND>; + clock-names = "nand"; }; ethsys: syscon@1e000000 { @@ -398,8 +389,9 @@ ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; - clocks = <&sysclock>; - clock-names = "ethif"; + clocks = <&pll MT7621_CLK_FE>, + <&pll MT7621_CLK_ETH>; + clock-names = "fe", "ethif"; #address-cells = <1>; #size-cells = <0>; @@ -532,7 +524,9 @@ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; + clocks = <&pll MT7621_CLK_PCIE0>, + <&pll MT7621_CLK_PCIE1>, + <&pll MT7621_CLK_PCIE2>; clock-names = "pcie0", "pcie1", "pcie2"; phys = <&pcie0_phy 1>, <&pcie2_phy 0>; phy-names = "pcie-phy0", "pcie-phy2";