| Message ID | 20201113121252.1433354-1-gregory.clement@bootlin.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | dt-bindings: pinctrl: ocelot: convert pinctrl bindings to json-schema | expand |
On Fri, Nov 13, 2020 at 01:12:46PM +0100, Gregory CLEMENT wrote: > Convert device tree bindings for Microsemi SoC (Ocelot, Luton, Serval, > Jguar2, Sarx5) Pin Controller to YAML format > > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 41 ------------ > .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 64 +++++++++++++++++++ > 2 files changed, 64 insertions(+), 41 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml Please resend Cc'ing Linus. > diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > new file mode 100644 > index 000000000000..b774b92becc8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > @@ -0,0 +1,64 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microsemi Ocelot pin controller Device Tree Bindings > + > +maintainers: > + - Alexandre Belloni <alexandre.belloni@bootlin.com> > + > +properties: > + compatible: > + enum: > + - microchip,sparx5-pinctrl > + - mscc,jaguar2-pinctrl > + - mscc,luton-pinctrl > + - mscc,ocelot-pinctrl > + - mscc,serval-pinctrl > + > + "#gpio-cells": > + const: 2 > + description: > + The first cell is the pin number and the second cell specifies > + GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + gpio-ranges: > + maxItems: 1 > + > +required: > + - "#gpio-cells" > + - compatible > + - reg > + - gpio-controller > + - gpio-ranges > + > +additionalProperties: false > + > +examples: > + - | > + gpio: pinctrl@71070034 { > + compatible = "mscc,ocelot-pinctrl"; > + reg = <0x71070034 0x28>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&gpio 0 0 22>; > + > + uart_pins: uart-pins { You need to define '-pins$' under patternProperties. Without it, this doesn't pass validation. > + pins = "GPIO_6", "GPIO_7"; > + function = "uart"; mixed tabs and spaces. YAML wants spaces. > + }; > + > + uart2_pins: uart2-pins { > + pins = "GPIO_12", "GPIO_13"; > + function = "uart2"; > + }; > + }; > + > +... > \ No newline at end of file Fix this.
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt deleted file mode 100644 index db99bd95d423..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ /dev/null @@ -1,41 +0,0 @@ -Microsemi Ocelot pin controller Device Tree Bindings ----------------------------------------------------- - -Required properties: - - compatible : Should be "mscc,ocelot-pinctrl", - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl" or "mscc,serval-pinctrl" - - reg : Address and length of the register set for the device - - gpio-controller : Indicates this device is a GPIO controller - - #gpio-cells : Must be 2. - The first cell is the pin number and the - second cell specifies GPIO flags, as defined in - <dt-bindings/gpio/gpio.h>. - - gpio-ranges : Range of pins managed by the GPIO controller. - - -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin -configuration documented in pinctrl-bindings.txt. - -The following generic properties are supported: - - function - - pins - -Example: - gpio: pinctrl@71070034 { - compatible = "mscc,ocelot-pinctrl"; - reg = <0x71070034 0x28>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio 0 0 22>; - - uart_pins: uart-pins { - pins = "GPIO_6", "GPIO_7"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - pins = "GPIO_12", "GPIO_13"; - function = "uart2"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml new file mode 100644 index 000000000000..b774b92becc8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi Ocelot pin controller Device Tree Bindings + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +properties: + compatible: + enum: + - microchip,sparx5-pinctrl + - mscc,jaguar2-pinctrl + - mscc,luton-pinctrl + - mscc,ocelot-pinctrl + - mscc,serval-pinctrl + + "#gpio-cells": + const: 2 + description: + The first cell is the pin number and the second cell specifies + GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. + + reg: + maxItems: 1 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + +required: + - "#gpio-cells" + - compatible + - reg + - gpio-controller + - gpio-ranges + +additionalProperties: false + +examples: + - | + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + }; + +... \ No newline at end of file
Convert device tree bindings for Microsemi SoC (Ocelot, Luton, Serval, Jguar2, Sarx5) Pin Controller to YAML format Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 41 ------------ .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 64 +++++++++++++++++++ 2 files changed, 64 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml