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Tue, 2 Mar 2021 02:29:21 +0000 From: YunQiang Su To: tsbogend@alpha.franken.de, macro@orcam.me.uk, jiaxun.yang@flygoat.com Cc: linux-mips@vger.kernel.org, YunQiang Su , stable@vger.kernel.org Subject: [PATCH v6] MIPS: force use FR=0 for FPXX binary Date: Tue, 2 Mar 2021 02:29:07 +0000 Message-Id: <20210302022907.1835-1-yunqiang.su@cipunited.com> X-Mailer: git-send-email 2.20.1 X-Originating-IP: [60.247.76.83] X-ClientProxiedBy: HK2PR02CA0153.apcprd02.prod.outlook.com (2603:1096:201:1f::13) To HKAPR04MB3956.apcprd04.prod.outlook.com (2603:1096:203:d5::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (60.247.76.83) by HK2PR02CA0153.apcprd02.prod.outlook.com (2603:1096:201:1f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3890.20 via Frontend Transport; Tue, 2 Mar 2021 02:29:20 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aeffc697-ae8d-4f4c-3014-08d8dd22fc78 X-MS-TrafficTypeDiagnostic: HK0PR04MB2705: X-MS-Exchange-MinimumUrlDomainAge: googlesource.com#5977 X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2399; 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X-MS-Exchange-AntiSpam-MessageData: 6Ca2+9E0zwCLxHYiGZwtp2GgwJiRjpNXufkgde2kjvegjHRfRXWIAxnWHBB0FHZ/AFASwHWejMZrK8GVXRq0pwSdaYrCfnvJsjGc7cLEPHSBImtP38k4OHLR5QmSFuTtAa2FiDanjn2xfazjiv2o+fcmgRmuMGB3KXS75nxlVkOKP0c0B0t87WXb1zaw96/m/yRK21/OrqbPHP2HkgPZQZfRXIrZpMaviLhUwuHG+fMKvtaE3M7zfwgI9+DU9+lpTK1qSjEV05Q+2sOL6miw5Ow8sxnvi76zSp6DJl/v2OcRsXgNE6ipyEUanScOKzWCU3M7SNM7NIYgLf3gnCMhHY0NitxlrO9HHmXVWjGbqV4AMFxUi1vxopiSI/d1VAnsAuyb4ke2IzvAAInZclScVSZrwj/2Th0KvdKxhaol/hTPoauEJgNNIkuklUgppEjy6Qlo9Jb310BrsK0dlHut9NF/qkWVOablHl7H/bZ6Lj7chKP/xSuW7DWbbxCQu+a+BUkwla9/3RDiQPQ1uPoFAwKQcyLqhcv38c3D6WcvI4Dwcl6NK0t8FGT0imQlrxKlesVpgs8JjUhKPD41o9BkXHXD53dpVGysg9wzIM4wzWbQ35bQGu+JxwBJo4cIMVM399wBdLT8QpIDw+aEb1KBy1WwQA7ZelMGkUUe7AZflUPwyIRMkAAewPyd8Uc3ysjWAxq6NYdYnPMrVg4ijnV2UDVhpiZEDr6iMLl/6T1eh62kF7ZsBnEqOvCus7uZeESwmvRF87+vVcfRnrzd+fbXFfUiorkcxWV84t8rMIAgfNq6QOGUcwhAdxWRvAkTpOwi2OzLfjHslkDnuQzdx40VeGVuRhW+IIxUltbPjh4khYZE6slA8i3wDKRTjJBzV/jpq/Bu4Xd4HooKPSIXdcUFG1nsMhbEXNi1S31thZ5Q4cs+Hm0EbkXYKwRIShQwuHwic1mmgMM09ZQQU2mMgodzTZ+og+aepthTovEVZ3jcmeliEAswKGSIpTUiMfkX5XYM9OdWNiBgCXO50AWFtCEvIwKpp+sdqQNNDfYF5Xn+9wg1uZGbMd0Hvl2dWFe2ElB/BcdATAPSXJJCq/DNK8g52m2l1duZFV526dtHS0meg9Ue5mapVgGgpNCs1QGTq7dh37BUe72XQDhriWveF4JGYXBcOXvlKulIoBDDhijKS3vhUkneCpXZS5mO/dwV/NL1dLqjT5vQk5hWYWQ9WuJbT2LxqdY/CI29sqGTh08JnC4qQtOPU5pgooXjCqijQv4kgmTVcpkkpDcTrWECp4R4beJTgFq1DgEsTwaU4MH4IFYukmvrTXkmB/O1JBzQiRq1 X-OriginatorOrg: cipunited.com X-MS-Exchange-CrossTenant-Network-Message-Id: aeffc697-ae8d-4f4c-3014-08d8dd22fc78 X-MS-Exchange-CrossTenant-AuthSource: HKAPR04MB3956.apcprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2021 02:29:21.0004 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: e31cf5b5-ee69-4d5f-9c69-edeeda2458c0 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DA+ggBJkoMBMFLsJe/X4X7p/8DAjHdvNUGB1tyPcMIsig8Kc45ojyWQWuu7JSXNwlN7GbI+GuS/Xow9K9+aBOS29GZeN459kQNtUDppc/Os= X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK0PR04MB2705 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The MIPS FPU may have 2 mode: FR=0: MIPS I style, odd-FPR can only be single, and even-FPR can be double. FR=1: all 32 FPR can be double. The binary may have 3 mode: FP32: can only work with FR=0 mode FPXX: can work with both FR=0 and FR=1 mode. FP64: can only work with FR=1 mode Some binary, for example the output of golang, may be mark as FPXX, while in fact they are FP32. Currently, FR=1 mode is used for all FPXX binary, it makes some wrong behivour of the binaries. Since FPXX binary can work with both FR=1 and FR=0, we force it to use FR=0. Reference: https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking https://go-review.googlesource.com/c/go/+/239217 https://go-review.googlesource.com/c/go/+/237058 Signed-off-by: YunQiang Su Cc: stable@vger.kernel.org # 4.19+ v5->v6: Rollback to V3, aka remove config option. v4->v5: Fix CONFIG_MIPS_O32_FPXX_USE_FR0 usage: if -> ifdef v3->v4: introduce a config option: CONFIG_MIPS_O32_FPXX_USE_FR0 v2->v3: commit message: add Signed-off-by and Cc to stable. v1->v2: Fix bad commit message: in fact, we are switching to FR=0 --- arch/mips/kernel/elf.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c index 7b045d2a0b51..d1aa907e9864 100644 --- a/arch/mips/kernel/elf.c +++ b/arch/mips/kernel/elf.c @@ -234,9 +234,10 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr, * fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU * instructions so we don't care about the mode. We will simply use * the one preferred by the hardware. In fpxx case, that ABI can - * handle both FR=1 and FR=0, so, again, we simply choose the one - * preferred by the hardware. Next, if we only use single-precision - * FPU instructions, and the default ABI FPU mode is not good + * handle both FR=1 and FR=0. Here, we may need to use FR=0, because + * some binaries may be mark as FPXX by mistake (ie, output of golang). + * - If we only use single-precision FPU instructions, + * and the default ABI FPU mode is not good * (ie single + any ABI combination), we set again the FPU mode to the * one is preferred by the hardware. Next, if we know that the code * will only use single-precision instructions, shown by single being @@ -248,8 +249,9 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr, */ if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) state->overall_fp_mode = FP_FRE; - else if ((prog_req.fr1 && prog_req.frdefault) || - (prog_req.single && !prog_req.frdefault)) + else if (prog_req.fr1 && prog_req.frdefault) + state->overall_fp_mode = FP_FR0; + else if (prog_req.single && !prog_req.frdefault) /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */ state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) && cpu_has_mips_r2_r6) ?