diff mbox series

[2/3] MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling

Message ID 20210305100310.26627-3-huangpei@loongson.cn (mailing list archive)
State Superseded
Headers show
Series [1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table | expand

Commit Message

Huang Pei March 5, 2021, 10:03 a.m. UTC 
+. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached

+. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit

CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field.

+. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 48,
only save 48 - 12 + 5(for bit[63:59]) = 41 bits, aka. :

   bit[63:59] | 0000 0000 000 |  bit[47:12] | 0000 0000 0000

+. for CKSEG0, only save 29 - 12 = 17 bits

Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
 arch/mips/Kconfig    |  3 ++-
 arch/mips/mm/tlbex.c | 18 +++++++++++++++---
 2 files changed, 17 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2000bb2b0220..5741dae35b74 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2142,7 +2142,8 @@  config CPU_SUPPORTS_HUGEPAGES
 	depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
 config MIPS_PGD_C0_CONTEXT
 	bool
-	default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
+	depends on 64BIT
+	default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
 
 #
 # Set to y for ptrace access to watch registers.
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a7521b8f7658..7d89e016076e 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -848,8 +848,14 @@  void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
 		/* Clear lower 23 bits of context. */
 		uasm_i_dins(p, ptr, 0, 0, 23);
 
-		/* 1 0	1 0 1  << 6  xkphys cached */
+		/* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */
+#ifdef CONFIG_CPU_LOONGSON64
+		/* 0x98xx xxxx xxxx xxxx, bit[63:59]: 1 0 0 1 1 << 6, xphys cached */
+		uasm_i_ori(p, ptr, ptr, 0x4c0);
+#else
+		/* 0xa8xx xxxx xxxx xxxx, bit[63:59]: 1 0 1 0 1 << 6, xphys cached */
 		uasm_i_ori(p, ptr, ptr, 0x540);
+#endif
 		uasm_i_drotr(p, ptr, ptr, 11);
 #elif defined(CONFIG_SMP)
 		UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
@@ -1164,8 +1170,15 @@  build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
 
 	if (pgd_reg == -1) {
 		vmalloc_branch_delay_filled = 1;
-		/* 1 0	1 0 1  << 6  xkphys cached */
+		/* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */
+#ifdef CONFIG_CPU_LOONGSON64
+		/* 0x98xx xxxx xxxx xxxx, bit[63:59]: 1 0 0 1 1 << 6, xphys cached */
+		uasm_i_ori(p, ptr, ptr, 0x4c0);
+#else
+		/* 0xa8xx xxxx xxxx xxxx, bit[63:59]: 1 0 1 0 1 << 6, xphys cached */
 		uasm_i_ori(p, ptr, ptr, 0x540);
+#endif
+
 		uasm_i_drotr(p, ptr, ptr, 11);
 	}
 
@@ -1292,7 +1305,6 @@  build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
 
 	return rv;
 }
-
 /*
  * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
  * because EXL == 0.  If we wrap, we can also use the 32 instruction