| Message ID | 20210313013927.26733-2-huangpei@loongson.cn (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | c6972fb9ba8aab384568665411015b7deb8a8609 |
| Headers | show |
| Series | MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling | expand |
On Sat, Mar 13, 2021 at 09:39:27AM +0800, Huang Pei wrote: > +. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached, instread of > 0xa8xx_xxxx_xxxx_xxxx > > +. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit > > +. cast CAC_BASE into u64 to silence warning on MIPS32 > > CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field. > > +. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 53, > only save 53 - 12 = 41 bits, aka : > > bit[63:59] | 0000 00 | bit[53:12] | 0000 0000 0000 > > +. for CKSEG0, only save 29 - 12 = 17 bits > > when switching pgd, only need to save bit[53:12] or bit[28:12] into > CP0 Context's bit[63:23], see folling asm generated at run time > > tlbmiss_handler_setup_pgd: > .set push > .set noreorder > > dsra a2, a0, 29 > move a3, a0 > dins a0, zero, 29, 35 > daddiu a2, a2, 4 //for CKSEG0, a2 from 0xfffffffffffffffc > //into 0 > > movn a0, a3, a2 > dsll a0, a0, 11 > jr ra > dmtc0 a0, CP0_CONTEXT > > .set pop > > when using it on page walking > > dmfc0 k0, CP0_CONTEXT > dins k0, zero, 0, 23 // zero badv2 > ori k0, k0, (CAC_BASE >> 53) // *prefix* with bit[63:59] > drotr k0, k0, 11 // kick it in the right place > > Signed-off-by: Huang Pei <huangpei@loongson.cn> > --- > arch/mips/Kconfig | 3 ++- > arch/mips/mm/tlbex.c | 9 +++++---- > 2 files changed, 7 insertions(+), 5 deletions(-) applied to mips-next. Thomas.
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2000bb2b0220..5741dae35b74 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2142,7 +2142,8 @@ config CPU_SUPPORTS_HUGEPAGES depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA)) config MIPS_PGD_C0_CONTEXT bool - default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP + depends on 64BIT + default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP # # Set to y for ptrace access to watch registers. diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index a7521b8f7658..cfaf710096c9 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -848,8 +848,8 @@ void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* Clear lower 23 bits of context. */ uasm_i_dins(p, ptr, 0, 0, 23); - /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_ori(p, ptr, ptr, 0x540); + /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ + uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); uasm_i_drotr(p, ptr, ptr, 11); #elif defined(CONFIG_SMP) UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); @@ -1164,8 +1164,9 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, if (pgd_reg == -1) { vmalloc_branch_delay_filled = 1; - /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_ori(p, ptr, ptr, 0x540); + /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ + uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); + uasm_i_drotr(p, ptr, ptr, 11); }
+. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached, instread of 0xa8xx_xxxx_xxxx_xxxx +. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit +. cast CAC_BASE into u64 to silence warning on MIPS32 CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field. +. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 53, only save 53 - 12 = 41 bits, aka : bit[63:59] | 0000 00 | bit[53:12] | 0000 0000 0000 +. for CKSEG0, only save 29 - 12 = 17 bits when switching pgd, only need to save bit[53:12] or bit[28:12] into CP0 Context's bit[63:23], see folling asm generated at run time tlbmiss_handler_setup_pgd: .set push .set noreorder dsra a2, a0, 29 move a3, a0 dins a0, zero, 29, 35 daddiu a2, a2, 4 //for CKSEG0, a2 from 0xfffffffffffffffc //into 0 movn a0, a3, a2 dsll a0, a0, 11 jr ra dmtc0 a0, CP0_CONTEXT .set pop when using it on page walking dmfc0 k0, CP0_CONTEXT dins k0, zero, 0, 23 // zero badv2 ori k0, k0, (CAC_BASE >> 53) // *prefix* with bit[63:59] drotr k0, k0, 11 // kick it in the right place Signed-off-by: Huang Pei <huangpei@loongson.cn> --- arch/mips/Kconfig | 3 ++- arch/mips/mm/tlbex.c | 9 +++++---- 2 files changed, 7 insertions(+), 5 deletions(-)