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Mon, 22 Mar 2021 01:29:17 +0000 From: YunQiang Su To: linux-mips@vger.kernel.org Cc: macro@orcam.me.uk, jiaxun.yang@flygoat.com, f4bug@amsat.org, tsbogend@alpha.franken.de, YunQiang Su , stable@vger.kernel.org Subject: [PATCH v8] MIPS: force use FR=0 for FPXX binaries Date: Mon, 22 Mar 2021 01:28:59 +0000 Message-Id: <20210322012859.17083-1-yunqiang.su@cipunited.com> X-Mailer: git-send-email 2.20.1 X-Originating-IP: [60.247.76.83] X-ClientProxiedBy: HK2PR06CA0004.apcprd06.prod.outlook.com (2603:1096:202:2e::16) To HKAPR04MB3956.apcprd04.prod.outlook.com (2603:1096:203:d5::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (60.247.76.83) by HK2PR06CA0004.apcprd06.prod.outlook.com (2603:1096:202:2e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18 via Frontend Transport; Mon, 22 Mar 2021 01:29:16 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f7f95edb-08ae-4654-6312-08d8ecd1e8ed X-MS-TrafficTypeDiagnostic: HK2PR0401MB1953: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; 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X-MS-Exchange-AntiSpam-MessageData: k5IahIS89LpVoYCI6Y+CmoSvJWxOiDZNrNxyPLixN0q1bUAYv1+JPXm3SAGkPPeEo9M3266TbmYbxhd58uWjC77/H7Bp6Zmk96GALnrvngA2vdZtsnDB6FfS9EsJh6icDPrIV/D317MHeRJfDjJ8J5jUZ6wEOZaA4hXP8f3S6RWVSzORh6mZEUxRDSozX33QIgcUzhNX7kr3AbRXeMrYVcqCDPTXkQwy/DyDfat3zkLU66YRx9o2nnab/Z2cONr7hSRjVmLmKpaTbnJLEMZJDvCnxRMEIzDZJKrV5Av2g8csvC1YLpqsVu9Q8/qswnc/Zmt79gVZrRuYL46eY/KqiMTP+yjUk1T2uD4IeS1g0PDGeN7va60pwKQApKPa8hDd/epx+tpjUruVqov+9oFsjIR65KuR6otAgQxHKhOXfGC9Qjwi3WlltF92UURFsXf/qZElrTArOB7kvxGWRK8Yi7TCAmF4eLJ2sNkFf27bqT0tzcYyXededY4IQAcPGR5ZpEbjEAhrP1uqt/ruiMGuRoOUjZ/La8Q4LRwUMxVYJ9r+rhc19NcAapSCqxp1G2u61z1ADQsA6PKzL6NDzos5P9zCDeOMvn3WfBH4EdNn/NG8os8E2TV8tnbfYaXgU+3Xz19SXjSgt1ohQxd/A8j5RSzVhwEE22xFCYVzDwgvLqdXlxX3AbTEcQa4B0/i8MO7QvbeLKFJ6HnrvXb7mIRM/4FK0lROhZpFfgksYNttlKZsPprE4VLA6Nzvj9zcPx3Dte0GTTj1syAMfcv7Ru7boMb+/tOsj0za9OYonsx1qmsA4r7YqlCrlP6RXEp1Mk4gR36CLQPn2AV3LGgOTFjVt0ECD/fxstbtETgdEgzm304wHq1+doU4aXjloCgTxVclqOCF08D48XysSrvcTgBqX5dHs5/mBrvIR2Cu+Qg06NfPOXZYTiP/BRxEn7Z2lUmFXvDLSyVYsmAN9qIOS7gNoTQxChduypwHAskzvI5+VKRyzAD2CUauAFpCc1ku1GlxyPKOZmvuCi79EDTbd8EGg5PjoVjStNJ7sNKssE3xtRZpII2Hk3YIyNv21UWj7be+Mfk73l/NsrDsW/BSqAkVB1Zgep1QJ39RsPojVxzPGxyZyKf9cSRVEP4sE+2s3cG/y0t6Y3XAvpB0z7wjAD44vP9Ma51bB73tP5rAFufZWClzItufZo0rpD3h7apqe5o/zS3ByPl3Sj55o8kPfffA/8c2KatXkR5HLTZyRt+JUOZHTGBmyHeqH1asKZvVz1+iDP0SpDrf7/PjBysz0PzS4UyBhtamcFxVLFsMo3z7ttW43D1pXTkVurh69Vrq++s6 X-OriginatorOrg: cipunited.com X-MS-Exchange-CrossTenant-Network-Message-Id: f7f95edb-08ae-4654-6312-08d8ecd1e8ed X-MS-Exchange-CrossTenant-AuthSource: HKAPR04MB3956.apcprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2021 01:29:17.4341 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: e31cf5b5-ee69-4d5f-9c69-edeeda2458c0 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kTxXyzGom2Hd/c15mEsjMcXc06uaZOCt0pK08O66yXp4V4L0Cc7r0AleKSeYyv4ZirGdo0SfExjyatwmJXq/Ly/Fa81ROy8K1T73JKid7Aw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK2PR0401MB1953 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The MIPS FPU may have 3 mode: FR=0: MIPS I style, all of the FPR are single. FR=1: all 32 FPR can be double. FRE: redirecting the rw of odd-FPR to the upper 32bit of even-double FPR. The binary may have 3 mode: FP32: can only work with FR=0 and FRE mode FPXX: can work with all of FR=0/FR=1/FRE mode. FP64: can only work with FR=1 mode Some binary, for example the output of golang, may be mark as FPXX, while in fact they are FP32. It is caused by the bug of design and linker: Object produced by pure Go has no FP annotation while in fact they are FP32; if we link them with the C module which marked as FPXX, the result will be marked as FPXX. If these fake-FPXX binaries is executed in FR=1 mode, some problem will happen. In Golang, now we add the FP32 annotation, so the future golang programs won't have this problem. While for the existing binaries, we need a kernel workaround. Currently, FR=1 mode is used for all FPXX binary if O32_FP64 supported is enabled, it makes some wrong behivour of the binaries. Since FPXX binary can work with both FR=1 and FR=0, we force it to use FR=0. Reference: https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking https://go-review.googlesource.com/c/go/+/239217 https://go-review.googlesource.com/c/go/+/237058 Signed-off-by: YunQiang Su Cc: stable@vger.kernel.org # 4.19+ --- arch/mips/kernel/elf.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c index 7b045d2a0b51..311c4fde910d 100644 --- a/arch/mips/kernel/elf.c +++ b/arch/mips/kernel/elf.c @@ -232,11 +232,16 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr, * that inherently require the hybrid FP mode. * - If FR1 and FRDEFAULT is true, that means we hit the any-abi or * fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU - * instructions so we don't care about the mode. We will simply use - * the one preferred by the hardware. In fpxx case, that ABI can - * handle both FR=1 and FR=0, so, again, we simply choose the one - * preferred by the hardware. Next, if we only use single-precision - * FPU instructions, and the default ABI FPU mode is not good + * instructions so we don't care about the mode. + * In fpxx case, that ABI can handle all of FR=1/FR=0/FRE mode. + * Here, we need to use FR=0 mode instead of FR=1, because some binaries + * may be mark as FPXX by mistake due to bugs of design and linker: + * The object produced by pure Go has no FP annotation, + * then is treated as any-ABI by linker, although in fact they are FP32; + * if any-ABI object is linked with FPXX object, the result will be mark as FPXX. + * Then the problem happens: run FP32 binaries in FR=1 mode. + * - If we only use single-precision FPU instructions, + * and the default ABI FPU mode is not good * (ie single + any ABI combination), we set again the FPU mode to the * one is preferred by the hardware. Next, if we know that the code * will only use single-precision instructions, shown by single being @@ -248,8 +253,9 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr, */ if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) state->overall_fp_mode = FP_FRE; - else if ((prog_req.fr1 && prog_req.frdefault) || - (prog_req.single && !prog_req.frdefault)) + else if (prog_req.fr1 && prog_req.frdefault) + state->overall_fp_mode = FP_FR0; + else if (prog_req.single && !prog_req.frdefault) /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */ state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) && cpu_has_mips_r2_r6) ?