| Message ID | 20210425130915.31001-1-maoxiaochuan@loongson.cn (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1] MIPS:DTS:Correct device id of pcie for Loongnon-2K | expand |
在 2021/4/25 21:09, Xiaochuan Mao 写道: > from Loongson-2K user manual know that Loongson-2K have two > pcie controller pcie0 and pcie1, pcie0 have four port named port0~port3 > and pcie1 have 2 port named port0~port1. the device id of port0 is 7a19 > in each pcie controller and others are 7a09. > > Signed-off-by: Xiaochuan Mao <maoxiaochuan@loongson.cn> > --- > v1: > revert class code Could you please help me check the actual hardware? TBH I remeber I filled it with actual hardware values. Btw the tittle should be prefixed with [PATCH v2] You may generate version suffix with `git format-patch -v2` or try to utilize patch management tools like git-publish[1]. Thanks. [1]: https://github.com/stefanha/git-publish - Jiaxun > --- [...]
On 2021/4/25 下午9:49, Jiaxun Yang wrote: > > 在 2021/4/25 21:09, Xiaochuan Mao 写道: >> from Loongson-2K user manual know that Loongson-2K have two >> pcie controller pcie0 and pcie1, pcie0 have four port named port0~port3 >> and pcie1 have 2 port named port0~port1. the device id of port0 is 7a19 >> in each pcie controller and others are 7a09. >> >> Signed-off-by: Xiaochuan Mao <maoxiaochuan@loongson.cn> >> --- >> v1: >> revert class code > > > Could you please help me check the actual hardware? > > TBH I remeber I filled it with actual hardware values. here is the pci info on the board: pci_device_match_ids: vendor:0014, device:7A03, class:00020000 , devfn:00001800 pci_device_match_ids: vendor:0014, device:7A03, class:00020000 , devfn:00001900 pci_device_match_ids: vendor:0014, device:7A04, class:000C0380 , devfn:00002000 pci_device_match_ids: vendor:0014, device:7A14, class:000C0320 , devfn:00002100 pci_device_match_ids: vendor:0014, device:7A24, class:000C0310 , devfn:00002200 pci_device_match_ids: vendor:0014, device:7A05, class:00030200 , devfn:00002800 pci_device_match_ids: vendor:0014, device:7A06, class:00030000 , devfn:00003000 pci_device_match_ids: vendor:0014, device:7A07, class:00040300 , devfn:00003800 pci_device_match_ids: vendor:0014, device:7A08, class:00010601 , devfn:00004000 pci_device_match_ids: vendor:0014, device:7A19, class:00060400 , devfn:00004800 pci_device_match_ids: vendor:0014, device:7A09, class:00060400 , devfn:00005000 pci_device_match_ids: vendor:0014, device:7A09, class:00060400 , devfn:00005800 pci_device_match_ids: vendor:0014, device:7A09, class:00060400 , devfn:00006000 pci_device_match_ids: vendor:0014, device:7A19, class:00060400 , devfn:00006800 > > Btw the tittle should be prefixed with [PATCH v2] > > You may generate version suffix with `git format-patch -v2` or try to utilize patch management tools like git-publish[1]. > > Thanks. > > [1]: https://github.com/stefanha/git-publish > got it , thanks for suggest. I'll send v2. > - Jiaxun > > >> --- > > [...]
diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index 569e814def83..912dcad361ef 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -163,8 +163,8 @@ }; pci_bridge@a,0 { - compatible = "pci0014,7a19.0", - "pci0014,7a19", + compatible = "pci0014,7a09.0", + "pci0014,7a09", "pciclass060400", "pciclass0604"; @@ -178,8 +178,8 @@ }; pci_bridge@b,0 { - compatible = "pci0014,7a19.0", - "pci0014,7a19", + compatible = "pci0014,7a09.0", + "pci0014,7a09", "pciclass060400", "pciclass0604"; @@ -193,8 +193,8 @@ }; pci_bridge@c,0 { - compatible = "pci0014,7a19.0", - "pci0014,7a19", + compatible = "pci0014,7a09.0", + "pci0014,7a09", "pciclass060400", "pciclass0604"; @@ -223,8 +223,8 @@ }; pci_bridge@e,0 { - compatible = "pci0014,7a19.0", - "pci0014,7a19", + compatible = "pci0014,7a09.0", + "pci0014,7a09", "pciclass060400", "pciclass0604";
from Loongson-2K user manual know that Loongson-2K have two pcie controller pcie0 and pcie1, pcie0 have four port named port0~port3 and pcie1 have 2 port named port0~port1. the device id of port0 is 7a19 in each pcie controller and others are 7a09. Signed-off-by: Xiaochuan Mao <maoxiaochuan@loongson.cn> --- v1: revert class code --- .../boot/dts/loongson/loongson64-2k1000.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)