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[81.38.58.98]) by smtp.gmail.com with ESMTPSA id g17sm17539746wrh.72.2021.06.13.08.56.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jun 2021 08:56:26 -0700 (PDT) From: Sergio Paracuellos To: linux-staging@lists.linux.dev Cc: gregkh@linuxfoundation.org, neil@brown.name, linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, ilya.lipnitskiy@gmail.com, john@phrozen.org Subject: [PATCH 1/3] MIPS: ralink: Define PCI_IOBASE Date: Sun, 13 Jun 2021 17:56:21 +0200 Message-Id: <20210613155623.17233-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210613155623.17233-1-sergio.paracuellos@gmail.com> References: <20210613155623.17233-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org PCI_IOBASE is used to create VM maps for PCI I/O ports, it is required by generic PCI drivers to make memory mapped I/O range work. Hence define it for ralink architectures to be able to avoid parsing manually IO ranges in PCI generic driver code. Function 'plat_mem_setup' for ralink is using 'set_io_port_base' call using '0xa0000000' as address, so use the same address in the definition to align things. Signed-off-by: Sergio Paracuellos --- arch/mips/include/asm/mach-ralink/spaces.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/mips/include/asm/mach-ralink/spaces.h diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h new file mode 100644 index 000000000000..ec58d4a9ed05 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/spaces.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_RALINK_SPACES_H_ +#define __ASM_MACH_RALINK_SPACES_H_ + +#define PCI_IOBASE _AC(0xa0000000, UL) +#define PCI_IOSIZE SZ_16M +#define IO_SPACE_LIMIT (PCI_IOSIZE - 1) + +#include +#endif