diff mbox series

MIPS: MT extensions are not available on MIPS32r1

Message ID 20210625104929.42689-1-paul@crapouillou.net (mailing list archive)
State Accepted
Commit cad065ed8d8831df67b9754cc4437ed55d8b48c0
Headers show
Series MIPS: MT extensions are not available on MIPS32r1 | expand

Commit Message

Paul Cercueil June 25, 2021, 10:49 a.m. UTC
MIPS MT extensions were added with the MIPS 34K processor, which was
based on the MIPS32r2 ISA.

This fixes a build error when building a generic kernel for a MIPS32r1
CPU.

Fixes: c434b9f80b09 ("MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbol")
Cc: stable@vger.kernel.org # v5.9
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 arch/mips/include/asm/cpu-features.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Thomas Bogendoerfer June 29, 2021, 8:31 a.m. UTC | #1
On Fri, Jun 25, 2021 at 11:49:29AM +0100, Paul Cercueil wrote:
> MIPS MT extensions were added with the MIPS 34K processor, which was
> based on the MIPS32r2 ISA.
> 
> This fixes a build error when building a generic kernel for a MIPS32r1
> CPU.
> 
> Fixes: c434b9f80b09 ("MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbol")
> Cc: stable@vger.kernel.org # v5.9
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>  arch/mips/include/asm/cpu-features.h | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

applied to mips-next.

Thomas.
diff mbox series

Patch

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 78cf7e300f12..f98892fd8f1d 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -64,6 +64,8 @@ 
 	((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
 #define __isa_range_or_flag(ge, lt, flag) \
 	(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
+#define __isa_range_and_ase(ge, lt, ase) \
+	(__isa_range(ge, lt) && __ase(ase))
 
 /*
  * SMP assumption: Options of CPU 0 are a superset of all processors.
@@ -426,7 +428,7 @@ 
 #endif
 
 #ifndef cpu_has_mipsmt
-#define cpu_has_mipsmt		__isa_lt_and_ase(6, MIPS_ASE_MIPSMT)
+#define cpu_has_mipsmt		__isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
 #endif
 
 #ifndef cpu_has_vp