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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id a202sm16703279wmd.15.2021.09.25.13.32.31 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 25 Sep 2021 13:32:32 -0700 (PDT) From: Sergio Paracuellos To: tsbogend@alpha.franken.de Cc: robh@kernel.org, arnd@arndb.de, catalin.marinas@arm.com, Liviu.Dudau@arm.com, bhelgaas@google.com, matthias.bgg@gmail.com, gregkh@linuxfoundation.org, linux-mips@vger.kernel.org, linux-pci@vger.kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/6] staging: mt7621-pci: properly adjust base address for the IO window Date: Sat, 25 Sep 2021 22:32:24 +0200 Message-Id: <20210925203224.10419-7-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210925203224.10419-1-sergio.paracuellos@gmail.com> References: <20210925203224.10419-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The value to adjust in the bridge register RALINK_PCI_IOBASE must take into account the raw value from DT, not only the translated linux port number. As long as io_offset is zero, the two are the same, but if you were to use multiple host bridge in the system, or pick a different bus address in DT, you can have a nonzero io_offset. At this means to take into account the bus address which is used to calculate this offset, substracting it from the IO resource start address. Acked-by: Arnd Bergmann Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 6acfc94a16e7..503cb1fca2e0 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -482,7 +482,7 @@ static int mt7621_pcie_enable_ports(struct pci_host_bridge *host) /* Setup MEMWIN and IOWIN */ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); - pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE); + pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE); list_for_each_entry(port, &pcie->ports, list) { if (port->enabled) {