| Message ID | 20210930165741.9662-1-ilya.lipnitskiy@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 740da9d7ca4e25f5d87db9f80d75432681b61305 |
| Headers | show |
| Series | MIPS: Revert "add support for buggy MT7621S core detection" | expand |
On Thu, Sep 30, 2021 at 6:58 PM Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> wrote: > > This reverts commit 6decd1aad15f56b169217789630a0098b496de0e. CPULAUNCH > register is not set properly by some bootloaders, causing a regression > until a bootloader change is made, which is hard if not impossible on > some embedded devices. Revert the change until a more robust core > detection mechanism that works on MT7621S routers such as Netgear R6220 > as well as platforms like Digi EX15 can be made. > > Link: https://lore.kernel.org/lkml/4d9e3b39-7caa-d372-5d7b-42dcec36fec7@kernel.org > Fixes: 6decd1aad15f ("MIPS: add support for buggy MT7621S core detection") > Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> > --- > arch/mips/include/asm/mips-cps.h | 23 +---------------------- > 1 file changed, 1 insertion(+), 22 deletions(-) Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Thanks, Sergio Paracuellos > > diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h > index 35fb8ee6dd33..fd43d876892e 100644 > --- a/arch/mips/include/asm/mips-cps.h > +++ b/arch/mips/include/asm/mips-cps.h > @@ -10,8 +10,6 @@ > #include <linux/io.h> > #include <linux/types.h> > > -#include <asm/mips-boards/launch.h> > - > extern unsigned long __cps_access_bad_size(void) > __compiletime_error("Bad size for CPS accessor"); > > @@ -167,30 +165,11 @@ static inline uint64_t mips_cps_cluster_config(unsigned int cluster) > */ > static inline unsigned int mips_cps_numcores(unsigned int cluster) > { > - unsigned int ncores; > - > if (!mips_cm_present()) > return 0; > > /* Add one before masking to handle 0xff indicating no cores */ > - ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; > - > - if (IS_ENABLED(CONFIG_SOC_MT7621)) { > - struct cpulaunch *launch; > - > - /* > - * Ralink MT7621S SoC is single core, but the GCR_CONFIG method > - * always reports 2 cores. Check the second core's LAUNCH_FREADY > - * flag to detect if the second core is missing. This method > - * only works before the core has been started. > - */ > - launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); > - launch += 2; /* MT7621 has 2 VPEs per core */ > - if (!(launch->flags & LAUNCH_FREADY)) > - ncores = 1; > - } > - > - return ncores; > + return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; > } > > /** > -- > 2.33.0 >
On 1/10/21 2:57 am, Ilya Lipnitskiy wrote: > This reverts commit 6decd1aad15f56b169217789630a0098b496de0e. CPULAUNCH > register is not set properly by some bootloaders, causing a regression > until a bootloader change is made, which is hard if not impossible on > some embedded devices. Revert the change until a more robust core > detection mechanism that works on MT7621S routers such as Netgear R6220 > as well as platforms like Digi EX15 can be made. > > Link: https://lore.kernel.org/lkml/4d9e3b39-7caa-d372-5d7b-42dcec36fec7@kernel.org > Fixes: 6decd1aad15f ("MIPS: add support for buggy MT7621S core detection") > Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Acked-by: Greg Ungerer <gerg@kernel.org> Thanks Ilya for taking care of this. Regards Greg > --- > arch/mips/include/asm/mips-cps.h | 23 +---------------------- > 1 file changed, 1 insertion(+), 22 deletions(-) > > diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h > index 35fb8ee6dd33..fd43d876892e 100644 > --- a/arch/mips/include/asm/mips-cps.h > +++ b/arch/mips/include/asm/mips-cps.h > @@ -10,8 +10,6 @@ > #include <linux/io.h> > #include <linux/types.h> > > -#include <asm/mips-boards/launch.h> > - > extern unsigned long __cps_access_bad_size(void) > __compiletime_error("Bad size for CPS accessor"); > > @@ -167,30 +165,11 @@ static inline uint64_t mips_cps_cluster_config(unsigned int cluster) > */ > static inline unsigned int mips_cps_numcores(unsigned int cluster) > { > - unsigned int ncores; > - > if (!mips_cm_present()) > return 0; > > /* Add one before masking to handle 0xff indicating no cores */ > - ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; > - > - if (IS_ENABLED(CONFIG_SOC_MT7621)) { > - struct cpulaunch *launch; > - > - /* > - * Ralink MT7621S SoC is single core, but the GCR_CONFIG method > - * always reports 2 cores. Check the second core's LAUNCH_FREADY > - * flag to detect if the second core is missing. This method > - * only works before the core has been started. > - */ > - launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); > - launch += 2; /* MT7621 has 2 VPEs per core */ > - if (!(launch->flags & LAUNCH_FREADY)) > - ncores = 1; > - } > - > - return ncores; > + return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; > } > > /** >
On Thu, Sep 30, 2021 at 09:57:41AM -0700, Ilya Lipnitskiy wrote: > This reverts commit 6decd1aad15f56b169217789630a0098b496de0e. CPULAUNCH > register is not set properly by some bootloaders, causing a regression > until a bootloader change is made, which is hard if not impossible on > some embedded devices. Revert the change until a more robust core > detection mechanism that works on MT7621S routers such as Netgear R6220 > as well as platforms like Digi EX15 can be made. > > Link: https://lore.kernel.org/lkml/4d9e3b39-7caa-d372-5d7b-42dcec36fec7@kernel.org > Fixes: 6decd1aad15f ("MIPS: add support for buggy MT7621S core detection") > Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> > --- > arch/mips/include/asm/mips-cps.h | 23 +---------------------- > 1 file changed, 1 insertion(+), 22 deletions(-) applied to mips-fixes. Thomas.
diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h index 35fb8ee6dd33..fd43d876892e 100644 --- a/arch/mips/include/asm/mips-cps.h +++ b/arch/mips/include/asm/mips-cps.h @@ -10,8 +10,6 @@ #include <linux/io.h> #include <linux/types.h> -#include <asm/mips-boards/launch.h> - extern unsigned long __cps_access_bad_size(void) __compiletime_error("Bad size for CPS accessor"); @@ -167,30 +165,11 @@ static inline uint64_t mips_cps_cluster_config(unsigned int cluster) */ static inline unsigned int mips_cps_numcores(unsigned int cluster) { - unsigned int ncores; - if (!mips_cm_present()) return 0; /* Add one before masking to handle 0xff indicating no cores */ - ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; - - if (IS_ENABLED(CONFIG_SOC_MT7621)) { - struct cpulaunch *launch; - - /* - * Ralink MT7621S SoC is single core, but the GCR_CONFIG method - * always reports 2 cores. Check the second core's LAUNCH_FREADY - * flag to detect if the second core is missing. This method - * only works before the core has been started. - */ - launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - launch += 2; /* MT7621 has 2 VPEs per core */ - if (!(launch->flags & LAUNCH_FREADY)) - ncores = 1; - } - - return ncores; + return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; } /**
This reverts commit 6decd1aad15f56b169217789630a0098b496de0e. CPULAUNCH register is not set properly by some bootloaders, causing a regression until a bootloader change is made, which is hard if not impossible on some embedded devices. Revert the change until a more robust core detection mechanism that works on MT7621S routers such as Netgear R6220 as well as platforms like Digi EX15 can be made. Link: https://lore.kernel.org/lkml/4d9e3b39-7caa-d372-5d7b-42dcec36fec7@kernel.org Fixes: 6decd1aad15f ("MIPS: add support for buggy MT7621S core detection") Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> --- arch/mips/include/asm/mips-cps.h | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-)