From patchwork Fri Dec 17 18:39:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 12685509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F69BC433F5 for ; Fri, 17 Dec 2021 18:40:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237225AbhLQSkN (ORCPT ); Fri, 17 Dec 2021 13:40:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231750AbhLQSkN (ORCPT ); Fri, 17 Dec 2021 13:40:13 -0500 Received: from polaris.svanheule.net (polaris.svanheule.net [IPv6:2a00:c98:2060:a004:1::200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9CD1C061574 for ; Fri, 17 Dec 2021 10:40:12 -0800 (PST) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eafe:c901:ee0b:2663:4dc2:6747]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 0C311282A4F; Fri, 17 Dec 2021 19:40:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1639766411; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=H2SKZv6WDFCLBPFkqaOhYWcJOAHmG0CfGPXMaenmT9I=; b=4fjx/eTmy5rFM6PibdCaLrRa9ZnGxxHVkTiqfercqe1MCdGEOS7BQw0/Va81YvDn7j1qVh 4N0gKPutRwhP+VS1Fwnm7su68c5jXEFeO7T2bJzZUVCNVJSwQLOIRDQJHMQMA46mmGI/hv vZa7Np1VCvvFQofCY0//HU3uX+FcEy7U8cm3dglTrW9nx/OV9nEy0L0rJ4Cq/mru66e2ot HnThUgPI1FLs+q1VR8Ljp/mfzFU5aBGdzJoO/C94AkREOq3ltbBxWlwY9w71uZQElZx+jz E4LM3r9TK/LTf8Oru/dl6bNoV/NNKmDFwTzM5h3hRIPlslPq3EQLDvkG/acp8g== From: Sander Vanheule To: linux-mips@vger.kernel.org Cc: Paul Burton , Thomas Bogendoerfer , linux-kernel@vger.kernel.org, Sander Vanheule , INAGAKI Hiroshi Subject: [PATCH] MIPS: generic: enable SMP on SMVP systems Date: Fri, 17 Dec 2021 19:39:30 +0100 Message-Id: <20211217183930.16192-1-sander@svanheule.net> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org In addition to CPS SMP setups, also try to initialise MT SMP setups with multiple VPEs per CPU core. CMP SMP support is not provided as it is considered deprecated. Additionally, rework the code by dropping the err variable and make it similar to how other platforms perform this initialisation. Co-developed-by: INAGAKI Hiroshi Signed-off-by: INAGAKI Hiroshi Signed-off-by: Sander Vanheule --- arch/mips/generic/init.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c index 1842cddd8356..1d712eac1617 100644 --- a/arch/mips/generic/init.c +++ b/arch/mips/generic/init.c @@ -110,14 +110,15 @@ void __init plat_mem_setup(void) void __init device_tree_init(void) { - int err; - unflatten_and_copy_device_tree(); mips_cpc_probe(); - err = register_cps_smp_ops(); - if (err) - err = register_up_smp_ops(); + if (!register_cps_smp_ops()) + return; + if (!register_vsmp_smp_ops()) + return; + + register_up_smp_ops(); } int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,