From patchwork Sun Jan 15 12:19:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13102222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCB39C46467 for ; Sun, 15 Jan 2023 12:26:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231166AbjAOM0V (ORCPT ); Sun, 15 Jan 2023 07:26:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230327AbjAOM0T (ORCPT ); Sun, 15 Jan 2023 07:26:19 -0500 X-Greylist: delayed 409 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sun, 15 Jan 2023 04:26:19 PST Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 365E4869A for ; Sun, 15 Jan 2023 04:26:19 -0800 (PST) Received: from mars.. (unknown [109.129.72.247]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id C053F36BCF6; Sun, 15 Jan 2023 13:19:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1673785168; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=GylWQHxNMSx3z9vgXlhWrepYKY6jU2ekJkywNe2jEX4=; b=6E4YdKsZQitsWtlzGJzJC3pltB4po1sYhO/jUqAdlxOTaNF4Ql43YpT7EmR9jiwa1Hrg/Y FvX60N67EmqQqu8ZrdY+q1uuvizL2lh9USEuegFPj3Nautc2XjsUnUF489VZDwHWMp57T+ K15+NJFRShJ2fyAh2McNpArFLE28HlSHuDdFNceZsIx96BKs47j9sOnJRMbF9sYlT5o6Hm BvdP1FHhDsaNO/hRpteKzGicek6kuOFRpBl5uM7nxRxa9VVSM6P5u+4jOMbEwPuXVWucXv BcaEeGAGcOFu/xtJrURx4IYtatsb59S8ECUADHa0kGO2CWYtwUqebQ+sIZhtoQ== From: Sander Vanheule To: Thomas Bogendoerfer , linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule , Olliver Schinagl Subject: [PATCH] mips: Realtek RTL: select NO_EXCEPT_FILL Date: Sun, 15 Jan 2023 13:19:22 +0100 Message-Id: <20230115121922.6359-1-sander@svanheule.net> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The CPUs in these SoCs support MIPS32 R2, and allow ebase relocation. Even if the default exception base of 0x80000000 is used, the MIPS_GENERIC load address of 0x80100000 leaves sufficient space to not need an extra 0x400 bytes of padding. Suggested-by: Olliver Schinagl Signed-off-by: Sander Vanheule --- Olliver has suggested to make this change, in order to reduce the delta with a fully generic MIPS kernel. I hope the patch description makes sense, as I based the argumentation on the behaviour of the code, and similar commits 7d6d28377783 ("MIPS: Loongson64: select NO_EXCEPT_FILL") and dd54dedd947d ("MIPS: BCM47XX: select NO_EXCEPT_FILL"). The change was tested on an RTL8380 and an RTL8393 device, where it appears to work as expected. Best, Sander arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2db5c853992e..a8895aaa490e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -627,6 +627,7 @@ config MACH_REALTEK_RTL select IRQ_MIPS_CPU select CEVT_R4K select CSRC_R4K + select NO_EXCEPT_FILL select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_32BIT_KERNEL