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(ec2-18-163-35-77.ap-east-1.compute.amazonaws.com. [18.163.35.77]) by smtp.gmail.com with ESMTPSA id v12-20020a1709029a0c00b0019339f3368asm1493972plp.3.2023.02.09.05.28.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 05:28:09 -0800 (PST) From: Keguang Zhang To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Keguang Zhang Subject: [PATCH V2 1/3] dt-bindings: clock: Add Loongson-1 clock Date: Thu, 9 Feb 2023 21:26:12 +0800 Message-Id: <20230209132614.1079198-2-keguang.zhang@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230209132614.1079198-1-keguang.zhang@gmail.com> References: <20230209132614.1079198-1-keguang.zhang@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add devicetree binding document and related header file for the Loongson-1 clock. Signed-off-by: Keguang Zhang --- V1 -> V2: Change to one clock controller Add clock-related dt-binding header file Fix the warning of dt_binding_check --- .../bindings/clock/loongson,ls1x-clk.yaml | 49 +++++++++++++++++++ include/dt-bindings/clock/loongson,ls1x-clk.h | 19 +++++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml create mode 100644 include/dt-bindings/clock/loongson,ls1x-clk.h diff --git a/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml new file mode 100644 index 000000000000..a911762dd01a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 Clock Controller + +maintainers: + - Keguang Zhang + +properties: + compatible: + enum: + - loongson,ls1b-clk + - loongson,ls1c-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - "#clock-cells" + - compatible + - clocks + +additionalProperties: false + +examples: + - | + clkc: clock-controller@1fe78030 { + compatible = "loongson,ls1b-clk"; + reg = <0x1fe78030 0x8>; + + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/loongson,ls1x-clk.h b/include/dt-bindings/clock/loongson,ls1x-clk.h new file mode 100644 index 000000000000..579552c5f14b --- /dev/null +++ b/include/dt-bindings/clock/loongson,ls1x-clk.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson-1 clock tree IDs + * + * Copyright (C) 2023 Keguang Zhang + */ + +#ifndef __DT_BINDINGS_CLOCK_LS1X_CLK_H__ +#define __DT_BINDINGS_CLOCK_LS1X_CLK_H__ + +#define LS1X_CLKID_PLL 0 +#define LS1X_CLKID_CPU 1 +#define LS1X_CLKID_DC 2 +#define LS1X_CLKID_AHB 3 +#define LS1X_CLKID_APB 4 + +#define CLK_NR_CLKS (LS1X_CLKID_APB + 1) + +#endif /* __DT_BINDINGS_CLOCK_LS1X_CLK_H__ */