[4/5] MIPS: Loongson64: Remove CPU_HAS_WB

Commit Message

Jiaxun Yang Feb. 21, 2023, 1:16 p.m. UTC

Q: Do we have really have write buffer
A: Yes, on newer Loongson processors there is a "store fill buffer"
   that will collect *cached* writes, on all Loongson processors
   AXI crossbar will buffer all writes.

Q: Then why do we want to remove CPU_HAS_WB?
A: Because CPU_HAS_WB introduces wbflush, which intends to flush
   all write reuqests to mmio device. We won't be affected by store
   fill buffer because it won't buffer uncached writes. And a regular
   memory barrier is sufficient to flush crossbar write buffer.

Signed-off-by: Jiaxun Yang <[e-mail]>
---
 arch/mips/Kconfig            |  1 -
 arch/mips/loongson64/setup.c | 15 ---------------
 2 files changed, 16 deletions(-)

Patch

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 04a9a3889d75..04b09b82cb76 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -489,7 +489,6 @@  config MACH_LOONGSON64
 	select BOARD_SCACHE
 	select CSRC_R4K
 	select CEVT_R4K
-	select CPU_HAS_WB
 	select FORCE_PCI
 	select ISA
 	select I8259
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
index 3cd11c2b308b..257038e18779 100644
--- a/arch/mips/loongson64/setup.c
+++ b/arch/mips/loongson64/setup.c
@@ -6,7 +6,6 @@ 
 #include <linux/export.h>
 #include <linux/init.h>
 
-#include <asm/wbflush.h>
 #include <asm/bootinfo.h>
 #include <linux/libfdt.h>
 #include <linux/of_fdt.h>
@@ -17,20 +16,6 @@ 
 
 void *loongson_fdt_blob;
 
-static void wbflush_loongson(void)
-{
-	asm(".set\tpush\n\t"
-	    ".set\tnoreorder\n\t"
-	    ".set mips3\n\t"
-	    "sync\n\t"
-	    "nop\n\t"
-	    ".set\tpop\n\t"
-	    ".set mips0\n\t");
-}
-
-void (*__wbflush)(void) = wbflush_loongson;
-EXPORT_SYMBOL(__wbflush);
-
 void __init plat_mem_setup(void)
 {
 	if (loongson_fdt_blob)