| Message ID | 20230407223532.7981-1-jiaxun.yang@flygoat.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 74efddad96fb37f66906850da0ab9cca59446e49 |
| Headers | show |
| Series | MIPS: Limit MIPS_MT_SMP support by ISA reversion | expand |
On 4/7/23 15:35, Jiaxun Yang wrote: > MIPS MT ASE is only available on ISA between Release 1 and Release 5. > Add ISA level dependency to Kconfig to fix build. > > Reported-by: Guenter Roeck <linux@roeck-us.net> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> With this patch in place, I still get the second build failure. In file included from <command-line>: arch/mips/mm/init.c: In function 'mem_init': ././include/linux/compiler_types.h:397:45: error: call to '__compiletime_assert_437' declared with attribute error: BUILD_BUG_ON failed: IS_ENABLED(CONFIG_32BIT) && (_PFN_SHIFT > PAGE_SHIFT) 397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ ././include/linux/compiler_types.h:378:25: note: in definition of macro '__compiletime_assert' 378 | prefix ## suffix(); \ | ^~~~~~ ././include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert' 397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^~~~~~~~~~~~~~~~~~~ ./include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert' 39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) | ^~~~~~~~~~~~~~~~~~ ./include/linux/build_bug.h:50:9: note: in expansion of macro 'BUILD_BUG_ON_MSG' 50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) | ^~~~~~~~~~~~~~~~ arch/mips/mm/init.c:454:9: note: in expansion of macro 'BUILD_BUG_ON' 454 | BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (_PFN_SHIFT > PAGE_SHIFT)); Also, MIPS_MT_SMP is disabled, CONFIG_TARGET_ISA_REV=0, and CPU_MIPSR{1,2,6} is not set. Prior to "MIPS: generic: Enable all CPUs supported by virt board in Kconfig", the configuration was CONFIG_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_TARGET_ISA_REV=1 CONFIG_MIPS_MT_SMP=y Ultimately it is not my decision to make what should be enabled with mips:allmodconfig, but to me it looks like "MIPS: generic: Enable all CPUs supported by virt board in Kconfig" doesn't enable but disable various configurations. Thanks, Guenter > --- > arch/mips/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 5e399a5ac3b3..ecc7a755fae6 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -2194,7 +2194,8 @@ config CPU_R4K_CACHE_TLB > config MIPS_MT_SMP > bool "MIPS MT SMP support (1 TC on each available VPE)" > default y > - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS > + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6 > + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS > select CPU_MIPSR2_IRQ_VI > select CPU_MIPSR2_IRQ_EI > select SYNC_R4K
> 2023年4月8日 01:30，Guenter Roeck <linux@roeck-us.net> 写道： > > On 4/7/23 15:35, Jiaxun Yang wrote: >> MIPS MT ASE is only available on ISA between Release 1 and Release 5. >> Add ISA level dependency to Kconfig to fix build. >> Reported-by: Guenter Roeck <linux@roeck-us.net> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > With this patch in place, I still get the second build failure. + Thomas Seems like PTE bits are overflowing again. Last time we trade PTE special against RIXI, now I think we need to decide between PTE special and hugepage? > > In file included from <command-line>: > arch/mips/mm/init.c: In function 'mem_init': > ././include/linux/compiler_types.h:397:45: error: call to '__compiletime_assert_437' declared with attribute error: BUILD_BUG_ON failed: IS_ENABLED(CONFIG_32BIT) && (_PFN_SHIFT > PAGE_SHIFT) > 397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > | ^ > ././include/linux/compiler_types.h:378:25: note: in definition of macro '__compiletime_assert' > 378 | prefix ## suffix(); \ > | ^~~~~~ > ././include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert' > 397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > | ^~~~~~~~~~~~~~~~~~~ > ./include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert' > 39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) > | ^~~~~~~~~~~~~~~~~~ > ./include/linux/build_bug.h:50:9: note: in expansion of macro 'BUILD_BUG_ON_MSG' > 50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) > | ^~~~~~~~~~~~~~~~ > arch/mips/mm/init.c:454:9: note: in expansion of macro 'BUILD_BUG_ON' > 454 | BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (_PFN_SHIFT > PAGE_SHIFT)); > > Also, MIPS_MT_SMP is disabled, CONFIG_TARGET_ISA_REV=0, and CPU_MIPSR{1,2,6} > is not set. Prior to "MIPS: generic: Enable all CPUs supported by virt board > in Kconfig", the configuration was > > CONFIG_CPU_MIPS32_R1=y > CONFIG_CPU_MIPS32=y > CONFIG_CPU_MIPSR1=y > CONFIG_TARGET_ISA_REV=1 > CONFIG_MIPS_MT_SMP=y > > Ultimately it is not my decision to make what should be enabled with > mips:allmodconfig, but to me it looks like "MIPS: generic: Enable all CPUs > supported by virt board in Kconfig" doesn't enable but disable various > configurations. Indeed, as R4000 has less features so it must disable more options. To get maximum coverage on allmodconfig I think we’d better set default CPU to MIPS64R2 which have more features and wider user base. Also default to build 64 bit kernel if it’s supported by CPU. Thanks. Jiaxun > > Thanks, > Guenter >
On Sat, Apr 08, 2023 at 11:10:32AM +0100, Jiaxun Yang wrote: > > > > 2023年4月8日 01:30，Guenter Roeck <linux@roeck-us.net> 写道： > > > > On 4/7/23 15:35, Jiaxun Yang wrote: > >> MIPS MT ASE is only available on ISA between Release 1 and Release 5. > >> Add ISA level dependency to Kconfig to fix build. > >> Reported-by: Guenter Roeck <linux@roeck-us.net> > >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > > > With this patch in place, I still get the second build failure. > > + Thomas > > Seems like PTE bits are overflowing again. I'm going to revert de34007751aaba992373f2d659001a846aeb8811, which just solves all new build problems in one go. Then we can try to come up with a usable solution. Thomas.
> 2023年4月8日 13:17，Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写道： > > On Sat, Apr 08, 2023 at 11:10:32AM +0100, Jiaxun Yang wrote: >> >> >>> 2023年4月8日 01:30，Guenter Roeck <linux@roeck-us.net> 写道： >>> >>> On 4/7/23 15:35, Jiaxun Yang wrote: >>>> MIPS MT ASE is only available on ISA between Release 1 and Release 5. >>>> Add ISA level dependency to Kconfig to fix build. >>>> Reported-by: Guenter Roeck <linux@roeck-us.net> >>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >>> >>> With this patch in place, I still get the second build failure. >> >> + Thomas >> >> Seems like PTE bits are overflowing again. > > I'm going to revert de34007751aaba992373f2d659001a846aeb8811, which just > solves all new build problems in one go. Then we can try to come up with > a usable solution. Setting default CPU back to MIPS32 (R2?) [1] should also solve all those build problems. However those problems are always here, just R4X00 didn’t get much care before. [1]: https://lore.kernel.org/linux-mips/20230408115936.6631-1-jiaxun.yang@flygoat.com/ Thanks - Jiaxun > > Thomas. > > -- > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a > good idea. [ RFC1925, 2.3 ]
On Fri, 7 Apr 2023, Jiaxun Yang wrote: > MIPS MT ASE is only available on ISA between Release 1 and Release 5. > Add ISA level dependency to Kconfig to fix build. Actually the MIPS MT ASE is explicitly from R2 onwards only[1] and it has *not* been withdrawn as at R6[2]. NB I was onboard with MTI when the MT ASE was introduced (I was a member of the 34K team, working on CPU bringup), so I know this stuff first hand. References: [1] "MIPS32 Architecture for Programmers, VolumeIV-f: The MIPS MT Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00378, Revision 1.00, September 28, 2005, Section 1.1 "Background", p. 1 [2] "MIPS32 Architecture For Programmers, Volume I-A: Introduction to the MIPS32 Architecture", Imagination Technologies LTD., Document Number: MD00082, Revision 6.01, August 20, 2014, Chapter 1 "About This Book", p. 12 Maciej
> 2023年5月16日 16:05，Maciej W. Rozycki <macro@orcam.me.uk> 写道： > > On Fri, 7 Apr 2023, Jiaxun Yang wrote: > >> MIPS MT ASE is only available on ISA between Release 1 and Release 5. >> Add ISA level dependency to Kconfig to fix build. > > Actually the MIPS MT ASE is explicitly from R2 onwards only[1] and it has > *not* been withdrawn as at R6[2]. Thanks for the info! I’m a little bit confused with relationship of MT and VP though, I thought VP suppressed MT, and they look conflicting, does it mean there are two possible ways of multithreading in R6? If so I’d probably rewrite cps-sec in uasm to take that into account, sigh. Thanks - Jiaxun > > NB I was onboard with MTI when the MT ASE was introduced (I was a member > of the 34K team, working on CPU bringup), so I know this stuff first hand. > > References: > > [1] "MIPS32 Architecture for Programmers, VolumeIV-f: The MIPS MT > Application-Specific Extension to the MIPS32 Architecture", MIPS > Technologies, Inc., Document Number: MD00378, Revision 1.00, > September 28, 2005, Section 1.1 "Background", p. 1 > > [2] "MIPS32 Architecture For Programmers, Volume I-A: Introduction to the > MIPS32 Architecture", Imagination Technologies LTD., Document Number: > MD00082, Revision 6.01, August 20, 2014, Chapter 1 "About This Book", > p. 12 > > Maciej
On Tue, 16 May 2023, Jiaxun Yang wrote: > > Actually the MIPS MT ASE is explicitly from R2 onwards only[1] and it has > > *not* been withdrawn as at R6[2]. > > Thanks for the info! > > I’m a little bit confused with relationship of MT and VP though, I thought VP > suppressed MT, and they look conflicting, does it mean there are two possible > ways of multithreading in R6? Hmm, interesting point. I would have thought you can have either but not both, however there is a note along with the description of CP0.Config3.MT in[1] that for R6 the bit has to be 0. That place and the description of the new CP0.Config5.VP bit seem the only mentions of MT ASE/Module removal with R6 and there is e.g. this paragraph for CP0.Wired: "Release 6 adds the Limit field. The intent of a non-zero value for this field is to place a limit on the number of wired entries in a TLB such that non-wired entries may be shared in a common physical TLB by multiple VPEs (as defined in the Multi-threading (MT) Module, Volume IV-f), or Guests and Root (see the Virtualization Module, Volume IV-i). For Release 6, if the Limit field is greater than 0, and a value greater than Limit is written to the Wired field, then the write is ignored." which explicitly refers to the MT ASE/Module in the context of R6 only. Revision 6.02 is the only MIPS32r6 privileged specification a copy of which I have, however it has this note in the revision history: "* Added CP0 VPControl for MT (new)" so I guess support for the MT ASE/Module was removed as an afterthought and then the architecture specification updated in a sloppy manner. And indeed the MIPS64r6 privileged specification confirms that, as I have copies or revisions 6.00 and 6.03, and the former has the MT ASE/Module still fully supported (and no mention of the CP0.Config5.VP bit nor the CP0.VPControl register) while the latter is similar to MIPS32 revision 6.02 document. > If so I’d probably rewrite cps-sec in uasm to take that into account, sigh. I guess you don't have to be concerned about R6 then. [1] "MIPS32 Architecture For Programmers, Vol. III: MIPS32 / microMIPS32 Privileged Resource Architecture", IMAGINATION TECHNOLOGIES, Document Number: MD00090, Revision 6.02, July 10, 2015, Table 9.67 "Config3 Register Field Descriptions", p. 251 Maciej
> 2023年5月16日 21:47，Maciej W. Rozycki <macro@orcam.me.uk> 写道： > > On Tue, 16 May 2023, Jiaxun Yang wrote: > >>> Actually the MIPS MT ASE is explicitly from R2 onwards only[1] and it has >>> *not* been withdrawn as at R6[2]. >> >> Thanks for the info! >> >> I’m a little bit confused with relationship of MT and VP though, I thought VP >> suppressed MT, and they look conflicting, does it mean there are two possible >> ways of multithreading in R6? > > Hmm, interesting point. I would have thought you can have either but not > both, however there is a note along with the description of CP0.Config3.MT > in[1] that for R6 the bit has to be 0. That place and the description of > the new CP0.Config5.VP bit seem the only mentions of MT ASE/Module removal > with R6 and there is e.g. this paragraph for CP0.Wired: I’ve heard back from hardware guys, the stated that MT and VP are exclusive but we should not assume VP as only multithreading implementation on R6 (in term of privileged architecture). Actually I7200 (nanoMIPS) follows R6 privileged spec (Config.AR = 2) but have MT implemented rather than VP. However they assured me that *application processor* level cores that is expected to run Linux in future will only implement VP, so we can omit combination of MT and R6 in kernel. Just perform some basic checks to prevent hardware guys change their mind in future. […] Thanks - Jiaxun
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5e399a5ac3b3..ecc7a755fae6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2194,7 +2194,8 @@ config CPU_R4K_CACHE_TLB config MIPS_MT_SMP bool "MIPS MT SMP support (1 TC on each available VPE)" default y - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6 + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select SYNC_R4K
MIPS MT ASE is only available on ISA between Release 1 and Release 5. Add ISA level dependency to Kconfig to fix build. Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)