| Message ID | 20230519195135.79600-1-jiaxun.yang@flygoat.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v4] mips: add <asm-generic/io.h> including | expand |
On Fri, May 19, 2023, at 21:51, Jiaxun Yang wrote: > With the adding, some default ioremap_xx methods defined in > asm-generic/io.h can be used. E.g the default ioremap_uc() returning > NULL. > > We also massaged various headers to avoid nested includes. > > Signed-off-by: Baoquan He <bhe@redhat.com> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > [jiaxun.yang@flygoat.com: Massage more headers, fix ioport defines] > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > Cc: Huacai Chen <chenhuacai@kernel.org> > Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> > Cc: linux-mips@vger.kernel.org > --- > Tested against qemu malta 34Kf, boston I6500, Loongson64, hopefully > everything is fine now. Thanks a lot for figuring this out! > > @@ -44,6 +42,11 @@ > # define __raw_ioswabq(a, x) (x) > # define ____raw_ioswabq(a, x) (x) > > +# define _ioswabb ioswabb > +# define _ioswabw ioswabw > +# define _ioswabl ioswabl > +# define _ioswabq ioswabq > + I'm missing something here, what are these macros used for in addition to the non-underscore versions? > +#define memset_io memset_io > static inline void memset_io(volatile void __iomem *addr, unsigned > char val, int count) > { > memset((void __force *) addr, val, count); > } > +#define memcpy_fromio memcpy_fromio > static inline void memcpy_fromio(void *dst, const volatile void > __iomem *src, int count) > { > memcpy(dst, (void __force *) src, count); > } > +#define memcpy_toio memcpy_toio > static inline void memcpy_toio(volatile void __iomem *dst, const void > *src, int count) > { > memcpy((void __force *) dst, src, count); These three could probably go away now, as they are identical to the asm-generic version. Not important though. > @@ -549,6 +555,47 @@ extern void (*_dma_cache_inv)(unsigned long start, > unsigned long size); > #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + > __CSR_32_ADJUST) = (v)) > #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + > __CSR_32_ADJUST)) > > + > +#define __raw_readb __raw_readb > +#define __raw_readw __raw_readw > +#define __raw_readl __raw_readl > +#define __raw_readq __raw_readq > +#define __raw_writeb __raw_writeb > +#define __raw_writew __raw_writew > +#define __raw_writel __raw_writel > +#define __raw_writeq __raw_writeq > + > +#define readb readb > +#define readw readw > +#define readl readl > +#define writeb writeb > +#define writew writew > +#define writel writel > + > +#define readsb readsb > +#define readsw readsw > +#define readsl readsl > +#define readsq readsq > +#define writesb writesb > +#define writesw writesw > +#define writesl writesl > +#define writesq writesq As far as I can tell, the readsq()/writesq() helpers are currently only defined on 64-bit, it's probably best to leave it that way. On most other architectures, we also don't define __raw_readq() and __raw_writeq() on 32-bit because they lose the atomicity that might be required for FIFO accesses, but the existing MIPS version has them, so changing those should be a separate patch after it can be shown to not break anything. Arnd
> 2023年5月19日 22:05，Arnd Bergmann <arnd@arndb.de> 写道： > > On Fri, May 19, 2023, at 21:51, Jiaxun Yang wrote: >> With the adding, some default ioremap_xx methods defined in >> asm-generic/io.h can be used. E.g the default ioremap_uc() returning >> NULL. >> >> We also massaged various headers to avoid nested includes. >> >> Signed-off-by: Baoquan He <bhe@redhat.com> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >> [jiaxun.yang@flygoat.com: Massage more headers, fix ioport defines] >> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> >> Cc: Huacai Chen <chenhuacai@kernel.org> >> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> >> Cc: linux-mips@vger.kernel.org >> --- >> Tested against qemu malta 34Kf, boston I6500, Loongson64, hopefully >> everything is fine now. > > Thanks a lot for figuring this out! >> >> @@ -44,6 +42,11 @@ >> # define __raw_ioswabq(a, x) (x) >> # define ____raw_ioswabq(a, x) (x) >> >> +# define _ioswabb ioswabb >> +# define _ioswabw ioswabw >> +# define _ioswabl ioswabl >> +# define _ioswabq ioswabq >> + > > I'm missing something here, what are these macros used for in addition > to the non-underscore versions? Since now {in,out}{bwlq} have a `_` in prefix, it needs a corresponding ioswab variant to work. > >> +#define memset_io memset_io >> static inline void memset_io(volatile void __iomem *addr, unsigned >> char val, int count) >> { >> memset((void __force *) addr, val, count); >> } >> +#define memcpy_fromio memcpy_fromio >> static inline void memcpy_fromio(void *dst, const volatile void >> __iomem *src, int count) >> { >> memcpy(dst, (void __force *) src, count); >> } >> +#define memcpy_toio memcpy_toio >> static inline void memcpy_toio(volatile void __iomem *dst, const void >> *src, int count) >> { >> memcpy((void __force *) dst, src, count); > > These three could probably go away now, as they are identical > to the asm-generic version. Not important though. Will update in a follow-up patch, I’m planing to do some cleanup for those headers later. > >> @@ -549,6 +555,47 @@ extern void (*_dma_cache_inv)(unsigned long start, >> unsigned long size); >> #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + >> __CSR_32_ADJUST) = (v)) >> #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + >> __CSR_32_ADJUST)) >> >> + >> +#define __raw_readb __raw_readb >> +#define __raw_readw __raw_readw >> +#define __raw_readl __raw_readl >> +#define __raw_readq __raw_readq >> +#define __raw_writeb __raw_writeb >> +#define __raw_writew __raw_writew >> +#define __raw_writel __raw_writel >> +#define __raw_writeq __raw_writeq >> + >> +#define readb readb >> +#define readw readw >> +#define readl readl >> +#define writeb writeb >> +#define writew writew >> +#define writel writel >> + >> +#define readsb readsb >> +#define readsw readsw >> +#define readsl readsl >> +#define readsq readsq >> +#define writesb writesb >> +#define writesw writesw >> +#define writesl writesl >> +#define writesq writesq > > As far as I can tell, the readsq()/writesq() helpers are currently > only defined on 64-bit, it's probably best to leave it that way. Will opt-out them on 32 bit build. > > On most other architectures, we also don't define __raw_readq() > and __raw_writeq() on 32-bit because they lose the atomicity that > might be required for FIFO accesses, but the existing MIPS version > has them, so changing those should be a separate patch after it > can be shown to not break anything. Current implementation of __raw_readq __raw_readq will check for CPU’s 64bit support and do a 64bit access if possible, it’s helpful for running 32 bit kernel on 64 bit CPUs. Thanks - Jiaxun > > Arnd
On 05/19/23 at 08:51pm, Jiaxun Yang wrote: > With the adding, some default ioremap_xx methods defined in > asm-generic/io.h can be used. E.g the default ioremap_uc() returning > NULL. > > We also massaged various headers to avoid nested includes. > > Signed-off-by: Baoquan He <bhe@redhat.com> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > [jiaxun.yang@flygoat.com: Massage more headers, fix ioport defines] > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > Cc: Huacai Chen <chenhuacai@kernel.org> > Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> > Cc: linux-mips@vger.kernel.org > --- > Tested against qemu malta 34Kf, boston I6500, Loongson64, hopefully > everything is fine now. Thanks a lot for fixing this, Jiaxun. > --- > arch/mips/include/asm/io.h | 65 +++++++++++++++++++++++++++++---- > arch/mips/include/asm/mmiowb.h | 4 +- > arch/mips/include/asm/smp-ops.h | 2 - > arch/mips/include/asm/smp.h | 4 +- > arch/mips/kernel/setup.c | 1 + > arch/mips/pci/pci-ip27.c | 3 ++ > 6 files changed, 64 insertions(+), 15 deletions(-) > > diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h > index cc28d207a061..8508d01fb75e 100644 > --- a/arch/mips/include/asm/io.h > +++ b/arch/mips/include/asm/io.h > @@ -15,7 +15,6 @@ > #define ARCH_HAS_IOREMAP_WC > > #include <linux/compiler.h> > -#include <linux/kernel.h> > #include <linux/types.h> > #include <linux/irqflags.h> > > @@ -28,7 +27,6 @@ > #include <asm-generic/iomap.h> > #include <asm/page.h> > #include <asm/pgtable-bits.h> > -#include <asm/processor.h> > #include <asm/string.h> > #include <mangle-port.h> > > @@ -44,6 +42,11 @@ > # define __raw_ioswabq(a, x) (x) > # define ____raw_ioswabq(a, x) (x) > > +# define _ioswabb ioswabb > +# define _ioswabw ioswabw > +# define _ioswabl ioswabl > +# define _ioswabq ioswabq > + > # define __relaxed_ioswabb ioswabb > # define __relaxed_ioswabw ioswabw > # define __relaxed_ioswabl ioswabl > @@ -129,6 +132,7 @@ static inline phys_addr_t virt_to_phys(const volatile void *x) > * almost all conceivable cases a device driver should not be using > * this function > */ > +#define phys_to_virt phys_to_virt > static inline void * phys_to_virt(unsigned long address) > { > return __va(address); > @@ -297,9 +301,9 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ > return pfx##ioswab##bwlq(__mem, __val); \ > } > > -#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \ > +#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax) \ > \ > -static inline void pfx##out##bwlq##p(type val, unsigned long port) \ > +static inline void pfx##out##bwlq(type val, unsigned long port) \ > { \ > volatile type *__addr; \ > type __val; \ > @@ -319,7 +323,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ > *__addr = __val; \ > } \ > \ > -static inline type pfx##in##bwlq##p(unsigned long port) \ > +static inline type pfx##in##bwlq(unsigned long port) \ > { \ > volatile type *__addr; \ > type __val; \ > @@ -361,11 +365,10 @@ __BUILD_MEMORY_PFX(__mem_, q, u64, 0) > #endif > > #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ > - __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \ > - __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p) > + __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0) > > #define BUILDIO_IOPORT(bwlq, type) \ > - __BUILD_IOPORT_PFX(, bwlq, type) \ > + __BUILD_IOPORT_PFX(_, bwlq, type) \ > __BUILD_IOPORT_PFX(__mem_, bwlq, type) > > BUILDIO_IOPORT(b, u8) > @@ -481,14 +484,17 @@ BUILDSTRING(l, u32) > BUILDSTRING(q, u64) > #endif > > +#define memset_io memset_io > static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) > { > memset((void __force *) addr, val, count); > } > +#define memcpy_fromio memcpy_fromio > static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) > { > memcpy(dst, (void __force *) src, count); > } > +#define memcpy_toio memcpy_toio > static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) > { > memcpy((void __force *) dst, src, count); > @@ -549,6 +555,47 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); > #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) > #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) > > + > +#define __raw_readb __raw_readb > +#define __raw_readw __raw_readw > +#define __raw_readl __raw_readl > +#define __raw_readq __raw_readq > +#define __raw_writeb __raw_writeb > +#define __raw_writew __raw_writew > +#define __raw_writel __raw_writel > +#define __raw_writeq __raw_writeq > + > +#define readb readb > +#define readw readw > +#define readl readl > +#define writeb writeb > +#define writew writew > +#define writel writel > + > +#define readsb readsb > +#define readsw readsw > +#define readsl readsl > +#define readsq readsq > +#define writesb writesb > +#define writesw writesw > +#define writesl writesl > +#define writesq writesq > + > +#define _inb _inb > +#define _inw _inw > +#define _inl _inl > +#define insb insb > +#define insw insw > +#define insl insl > + > +#define _outb _outb > +#define _outw _outw > +#define _outl _outl > +#define outsb outsb > +#define outsw outsw > +#define outsl outsl > + > + > /* > * Convert a physical pointer to a virtual kernel pointer for /dev/mem > * access > @@ -557,4 +604,6 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); > > void __ioread64_copy(void *to, const void __iomem *from, size_t count); > > +#include <asm-generic/io.h> > + > #endif /* _ASM_IO_H */ > diff --git a/arch/mips/include/asm/mmiowb.h b/arch/mips/include/asm/mmiowb.h > index a40824e3ef8e..cf27752fd220 100644 > --- a/arch/mips/include/asm/mmiowb.h > +++ b/arch/mips/include/asm/mmiowb.h > @@ -2,9 +2,9 @@ > #ifndef _ASM_MMIOWB_H > #define _ASM_MMIOWB_H > > -#include <asm/io.h> > +#include <asm/barrier.h> > > -#define mmiowb() iobarrier_w() > +#define mmiowb() wmb() > > #include <asm-generic/mmiowb.h> > > diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h > index 5719ff49eff1..a6941b7f0cc0 100644 > --- a/arch/mips/include/asm/smp-ops.h > +++ b/arch/mips/include/asm/smp-ops.h > @@ -13,8 +13,6 @@ > > #include <linux/errno.h> > > -#include <asm/mips-cps.h> > - > #ifdef CONFIG_SMP > > #include <linux/cpumask.h> > diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h > index aab8981bc32c..125c3494a010 100644 > --- a/arch/mips/include/asm/smp.h > +++ b/arch/mips/include/asm/smp.h > @@ -11,13 +11,11 @@ > #ifndef __ASM_SMP_H > #define __ASM_SMP_H > > -#include <linux/bitops.h> > +#include <linux/compiler.h> > #include <linux/linkage.h> > -#include <linux/smp.h> > #include <linux/threads.h> > #include <linux/cpumask.h> > > -#include <linux/atomic.h> > #include <asm/smp-ops.h> > > extern int smp_num_siblings; > diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c > index febdc5564638..f9f149928e46 100644 > --- a/arch/mips/kernel/setup.c > +++ b/arch/mips/kernel/setup.c > @@ -41,6 +41,7 @@ > #include <asm/sections.h> > #include <asm/setup.h> > #include <asm/smp-ops.h> > +#include <asm/mips-cps.h> > #include <asm/prom.h> > #include <asm/fw/fw.h> > > diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c > index d85cbf84e41c..973faea61cad 100644 > --- a/arch/mips/pci/pci-ip27.c > +++ b/arch/mips/pci/pci-ip27.c > @@ -7,6 +7,9 @@ > * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) > * Copyright (C) 1999, 2000 Silicon Graphics, Inc. > */ > + > +#include <linux/io.h> > + > #include <asm/sn/addrs.h> > #include <asm/sn/types.h> > #include <asm/sn/klconfig.h> > -- > 2.39.2 (Apple Git-143) >
On Fri, 19 May 2023, Arnd Bergmann wrote: > On most other architectures, we also don't define __raw_readq() > and __raw_writeq() on 32-bit because they lose the atomicity that > might be required for FIFO accesses, but the existing MIPS version > has them, so changing those should be a separate patch after it > can be shown to not break anything. With MIPS we have: if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ *__mem = __val; \ else if (cpu_has_64bits) { \ unsigned long __flags; \ type __tmp; \ \ if (irq) \ local_irq_save(__flags); \ __asm__ __volatile__( \ ".set push" "\t\t# __writeq""\n\t" \ ".set arch=r4000" "\n\t" \ "dsll32 %L0, %L0, 0" "\n\t" \ "dsrl32 %L0, %L0, 0" "\n\t" \ "dsll32 %M0, %M0, 0" "\n\t" \ "or %L0, %L0, %M0" "\n\t" \ "sd %L0, %2" "\n\t" \ ".set pop" "\n" \ : "=r" (__tmp) \ : "0" (__val), "m" (*__mem)); \ if (irq) \ local_irq_restore(__flags); \ } else \ BUG(); \ etc. so we don't actually lose atomicity, because we always use 64-bit operations (SD above, store-doubleword) and we BUG if they are not there (i.e. with 32-bit hardware; not a build-time check as in principle the same 32-bit kernel image ought to run just fine both on 32-bit and 64-bit hardware). A few MIPS platforms do use them, e.g. SB1250, which requires 64-bit unswapped accesses to SoC registers. Maciej
On Sat, May 20, 2023, at 16:45, Maciej W. Rozycki wrote: > if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ > *__mem = __val; \ > else if (cpu_has_64bits) { \ > unsigned long __flags; \ > type __tmp; \ > \ > if (irq) \ > local_irq_save(__flags); \ > __asm__ __volatile__( \ > ".set push" "\t\t# __writeq""\n\t" \ > ".set arch=r4000" "\n\t" \ > "dsll32 %L0, %L0, 0" "\n\t" \ > "dsrl32 %L0, %L0, 0" "\n\t" \ > "dsll32 %M0, %M0, 0" "\n\t" \ > "or %L0, %L0, %M0" "\n\t" \ > "sd %L0, %2" "\n\t" \ > ".set pop" "\n" \ > : "=r" (__tmp) \ > : "0" (__val), "m" (*__mem)); \ > if (irq) \ > local_irq_restore(__flags); \ > } else \ > BUG(); \ > > etc. so we don't actually lose atomicity, because we always use 64-bit > operations (SD above, store-doubleword) and we BUG if they are not there > (i.e. with 32-bit hardware; not a build-time check as in principle the > same 32-bit kernel image ought to run just fine both on 32-bit and 64-bit > hardware). A few MIPS platforms do use them, e.g. SB1250, which requires > 64-bit unswapped accesses to SoC registers. Ok, makes sense. Arnd
Hi Jiaxun,
kernel test robot noticed the following build warnings:
[auto build test WARNING on soc/for-next]
[also build test WARNING on linus/master v6.4-rc3 next-20230525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jiaxun-Yang/mips-add-asm-generic-io-h-including/20230520-035318
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link: https://lore.kernel.org/r/20230519195135.79600-1-jiaxun.yang%40flygoat.com
patch subject: [PATCH v4] mips: add <asm-generic/io.h> including
config: mips-randconfig-r015-20230525 (https://download.01.org/0day-ci/archive/20230526/202305261736.cBisGOAz-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project 4faf3aaf28226a4e950c103a14f6fc1d1fdabb1b)
reproduce (this is a W=1 build):
mkdir -p ~/bin
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install mips cross compiling tool for clang build
# apt-get install binutils-mips-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/4f10a6993ab8060829908b87cdeea41f7eae38e7
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jiaxun-Yang/mips-add-asm-generic-io-h-including/20230520-035318
git checkout 4f10a6993ab8060829908b87cdeea41f7eae38e7
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang ~/bin/make.cross W=1 O=build_dir ARCH=mips olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang ~/bin/make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash drivers/mmc/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202305261736.cBisGOAz-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/mmc/host/dw_mmc.c:41:
>> drivers/mmc/host/dw_mmc.h:506:9: warning: '__raw_writeq' macro redefined [-Wmacro-redefined]
#define __raw_writeq(__value, __reg) \
^
arch/mips/include/asm/io.h:566:9: note: previous definition is here
#define __raw_writeq __raw_writeq
^
In file included from drivers/mmc/host/dw_mmc.c:41:
>> drivers/mmc/host/dw_mmc.h:508:9: warning: '__raw_readq' macro redefined [-Wmacro-redefined]
#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
^
arch/mips/include/asm/io.h:562:9: note: previous definition is here
#define __raw_readq __raw_readq
^
2 warnings generated.
vim +/__raw_writeq +506 drivers/mmc/host/dw_mmc.h
76184ac17edf3c Ben Dooks 2015-03-25 473
f95f3850f7a9e1 Will Newton 2011-01-02 474 /* Register access macros */
f95f3850f7a9e1 Will Newton 2011-01-02 475 #define mci_readl(dev, reg) \
a2f17680f42878 Ben Dooks 2015-03-25 476 readl_relaxed((dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 477 #define mci_writel(dev, reg, value) \
a2f17680f42878 Ben Dooks 2015-03-25 478 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 479
f95f3850f7a9e1 Will Newton 2011-01-02 480 /* 16-bit FIFO access macros */
f95f3850f7a9e1 Will Newton 2011-01-02 481 #define mci_readw(dev, reg) \
a2f17680f42878 Ben Dooks 2015-03-25 482 readw_relaxed((dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 483 #define mci_writew(dev, reg, value) \
a2f17680f42878 Ben Dooks 2015-03-25 484 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 485
f95f3850f7a9e1 Will Newton 2011-01-02 486 /* 64-bit FIFO access macros */
f95f3850f7a9e1 Will Newton 2011-01-02 487 #ifdef readq
f95f3850f7a9e1 Will Newton 2011-01-02 488 #define mci_readq(dev, reg) \
a2f17680f42878 Ben Dooks 2015-03-25 489 readq_relaxed((dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 490 #define mci_writeq(dev, reg, value) \
a2f17680f42878 Ben Dooks 2015-03-25 491 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 492 #else
f95f3850f7a9e1 Will Newton 2011-01-02 493 /*
f95f3850f7a9e1 Will Newton 2011-01-02 494 * Dummy readq implementation for architectures that don't define it.
f95f3850f7a9e1 Will Newton 2011-01-02 495 *
f95f3850f7a9e1 Will Newton 2011-01-02 496 * We would assume that none of these architectures would configure
f95f3850f7a9e1 Will Newton 2011-01-02 497 * the IP block with a 64bit FIFO width, so this code will never be
f95f3850f7a9e1 Will Newton 2011-01-02 498 * executed on those machines. Defining these macros here keeps the
f95f3850f7a9e1 Will Newton 2011-01-02 499 * rest of the code free from ifdefs.
f95f3850f7a9e1 Will Newton 2011-01-02 500 */
f95f3850f7a9e1 Will Newton 2011-01-02 501 #define mci_readq(dev, reg) \
892b1e312b1791 James Hogan 2011-06-24 502 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
f95f3850f7a9e1 Will Newton 2011-01-02 503 #define mci_writeq(dev, reg, value) \
892b1e312b1791 James Hogan 2011-06-24 504 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
76184ac17edf3c Ben Dooks 2015-03-25 505
76184ac17edf3c Ben Dooks 2015-03-25 @506 #define __raw_writeq(__value, __reg) \
76184ac17edf3c Ben Dooks 2015-03-25 507 (*(volatile u64 __force *)(__reg) = (__value))
76184ac17edf3c Ben Dooks 2015-03-25 @508 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
f95f3850f7a9e1 Will Newton 2011-01-02 509 #endif
f95f3850f7a9e1 Will Newton 2011-01-02 510
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index cc28d207a061..8508d01fb75e 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -15,7 +15,6 @@ #define ARCH_HAS_IOREMAP_WC #include <linux/compiler.h> -#include <linux/kernel.h> #include <linux/types.h> #include <linux/irqflags.h> @@ -28,7 +27,6 @@ #include <asm-generic/iomap.h> #include <asm/page.h> #include <asm/pgtable-bits.h> -#include <asm/processor.h> #include <asm/string.h> #include <mangle-port.h> @@ -44,6 +42,11 @@ # define __raw_ioswabq(a, x) (x) # define ____raw_ioswabq(a, x) (x) +# define _ioswabb ioswabb +# define _ioswabw ioswabw +# define _ioswabl ioswabl +# define _ioswabq ioswabq + # define __relaxed_ioswabb ioswabb # define __relaxed_ioswabw ioswabw # define __relaxed_ioswabl ioswabl @@ -129,6 +132,7 @@ static inline phys_addr_t virt_to_phys(const volatile void *x) * almost all conceivable cases a device driver should not be using * this function */ +#define phys_to_virt phys_to_virt static inline void * phys_to_virt(unsigned long address) { return __va(address); @@ -297,9 +301,9 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ return pfx##ioswab##bwlq(__mem, __val); \ } -#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \ +#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax) \ \ -static inline void pfx##out##bwlq##p(type val, unsigned long port) \ +static inline void pfx##out##bwlq(type val, unsigned long port) \ { \ volatile type *__addr; \ type __val; \ @@ -319,7 +323,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ *__addr = __val; \ } \ \ -static inline type pfx##in##bwlq##p(unsigned long port) \ +static inline type pfx##in##bwlq(unsigned long port) \ { \ volatile type *__addr; \ type __val; \ @@ -361,11 +365,10 @@ __BUILD_MEMORY_PFX(__mem_, q, u64, 0) #endif #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ - __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \ - __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p) + __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0) #define BUILDIO_IOPORT(bwlq, type) \ - __BUILD_IOPORT_PFX(, bwlq, type) \ + __BUILD_IOPORT_PFX(_, bwlq, type) \ __BUILD_IOPORT_PFX(__mem_, bwlq, type) BUILDIO_IOPORT(b, u8) @@ -481,14 +484,17 @@ BUILDSTRING(l, u32) BUILDSTRING(q, u64) #endif +#define memset_io memset_io static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) { memset((void __force *) addr, val, count); } +#define memcpy_fromio memcpy_fromio static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) { memcpy(dst, (void __force *) src, count); } +#define memcpy_toio memcpy_toio static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) { memcpy((void __force *) dst, src, count); @@ -549,6 +555,47 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) + +#define __raw_readb __raw_readb +#define __raw_readw __raw_readw +#define __raw_readl __raw_readl +#define __raw_readq __raw_readq +#define __raw_writeb __raw_writeb +#define __raw_writew __raw_writew +#define __raw_writel __raw_writel +#define __raw_writeq __raw_writeq + +#define readb readb +#define readw readw +#define readl readl +#define writeb writeb +#define writew writew +#define writel writel + +#define readsb readsb +#define readsw readsw +#define readsl readsl +#define readsq readsq +#define writesb writesb +#define writesw writesw +#define writesl writesl +#define writesq writesq + +#define _inb _inb +#define _inw _inw +#define _inl _inl +#define insb insb +#define insw insw +#define insl insl + +#define _outb _outb +#define _outw _outw +#define _outl _outl +#define outsb outsb +#define outsw outsw +#define outsl outsl + + /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem * access @@ -557,4 +604,6 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); void __ioread64_copy(void *to, const void __iomem *from, size_t count); +#include <asm-generic/io.h> + #endif /* _ASM_IO_H */ diff --git a/arch/mips/include/asm/mmiowb.h b/arch/mips/include/asm/mmiowb.h index a40824e3ef8e..cf27752fd220 100644 --- a/arch/mips/include/asm/mmiowb.h +++ b/arch/mips/include/asm/mmiowb.h @@ -2,9 +2,9 @@ #ifndef _ASM_MMIOWB_H #define _ASM_MMIOWB_H -#include <asm/io.h> +#include <asm/barrier.h> -#define mmiowb() iobarrier_w() +#define mmiowb() wmb() #include <asm-generic/mmiowb.h> diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index 5719ff49eff1..a6941b7f0cc0 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -13,8 +13,6 @@ #include <linux/errno.h> -#include <asm/mips-cps.h> - #ifdef CONFIG_SMP #include <linux/cpumask.h> diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index aab8981bc32c..125c3494a010 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -11,13 +11,11 @@ #ifndef __ASM_SMP_H #define __ASM_SMP_H -#include <linux/bitops.h> +#include <linux/compiler.h> #include <linux/linkage.h> -#include <linux/smp.h> #include <linux/threads.h> #include <linux/cpumask.h> -#include <linux/atomic.h> #include <asm/smp-ops.h> extern int smp_num_siblings; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index febdc5564638..f9f149928e46 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -41,6 +41,7 @@ #include <asm/sections.h> #include <asm/setup.h> #include <asm/smp-ops.h> +#include <asm/mips-cps.h> #include <asm/prom.h> #include <asm/fw/fw.h> diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index d85cbf84e41c..973faea61cad 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -7,6 +7,9 @@ * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ + +#include <linux/io.h> + #include <asm/sn/addrs.h> #include <asm/sn/types.h> #include <asm/sn/klconfig.h>