Message ID | 20230816111310.1656224-4-keguang.zhang@gmail.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Move Loongson1 MAC arch-code to the driver dir | expand |
On Wed, Aug 16, 2023 at 07:13:09PM +0800, Keguang Zhang wrote: > This glue driver is created based on the arch-code > implemented earlier with the platform-specific settings. > > Use syscon for SYSCON register access. > > Partialy based on the previous work by Serge Semin. Hi Keguang Zhang, as it looks like there will be a v3 for other reasons, a minor nit from my side: Partialy -> Partially ...
> +static int ls1b_dwmac_syscon_init(struct plat_stmmacenet_data *plat) > +{ > + struct ls1x_dwmac *dwmac = plat->bsp_priv; > + struct regmap_field **regmap_fields = dwmac->regmap_fields; > + > + if (plat->bus_id) { > + regmap_field_write(regmap_fields[GMAC1_USE_UART1], 1); > + regmap_field_write(regmap_fields[GMAC1_USE_UART0], 1); > + > + switch (plat->phy_interface) { > + case PHY_INTERFACE_MODE_RGMII: > + regmap_field_write(regmap_fields[GMAC1_USE_TXCLK], 0); > + regmap_field_write(regmap_fields[GMAC1_USE_PWM23], 0); > + break; What about the other three RGMII modes? Plain rgmii is pretty unusual, rgmii-id is the most used. > + case PHY_INTERFACE_MODE_MII: > + regmap_field_write(regmap_fields[GMAC1_USE_TXCLK], 1); > + regmap_field_write(regmap_fields[GMAC1_USE_PWM23], 1); > + break; > + default: > + dev_err(dwmac->dev, "Unsupported PHY mode %u\n", > + plat->phy_interface); > + return -EOPNOTSUPP; > + } > + > + regmap_field_write(regmap_fields[GMAC1_SHUT], 0); > + } else { > + switch (plat->phy_interface) { > + case PHY_INTERFACE_MODE_RGMII: > + regmap_field_write(regmap_fields[GMAC0_USE_TXCLK], 0); > + regmap_field_write(regmap_fields[GMAC0_USE_PWM01], 0); > + break; same here. Andrew
On Sun, Aug 20, 2023 at 3:05 AM Simon Horman <horms@kernel.org> wrote: > > On Wed, Aug 16, 2023 at 07:13:09PM +0800, Keguang Zhang wrote: > > This glue driver is created based on the arch-code > > implemented earlier with the platform-specific settings. > > > > Use syscon for SYSCON register access. > > > > Partialy based on the previous work by Serge Semin. > > Hi Keguang Zhang, > > as it looks like there will be a v3 for other reasons, > a minor nit from my side: Partialy -> Partially > Will do. Thanks! > ...
On Mon, Aug 21, 2023 at 3:04 AM Andrew Lunn <andrew@lunn.ch> wrote: > > > +static int ls1b_dwmac_syscon_init(struct plat_stmmacenet_data *plat) > > +{ > > + struct ls1x_dwmac *dwmac = plat->bsp_priv; > > + struct regmap_field **regmap_fields = dwmac->regmap_fields; > > + > > + if (plat->bus_id) { > > + regmap_field_write(regmap_fields[GMAC1_USE_UART1], 1); > > + regmap_field_write(regmap_fields[GMAC1_USE_UART0], 1); > > + > > + switch (plat->phy_interface) { > > + case PHY_INTERFACE_MODE_RGMII: > > + regmap_field_write(regmap_fields[GMAC1_USE_TXCLK], 0); > > + regmap_field_write(regmap_fields[GMAC1_USE_PWM23], 0); > > + break; > > What about the other three RGMII modes? Plain rgmii is pretty unusual, > rgmii-id is the most used. > According to the LS1B datasheet, only RGMII and MII are supported. And I can confirm that MII mode does work for LS1B. > > + case PHY_INTERFACE_MODE_MII: > > + regmap_field_write(regmap_fields[GMAC1_USE_TXCLK], 1); > > + regmap_field_write(regmap_fields[GMAC1_USE_PWM23], 1); > > + break; > > + default: > > + dev_err(dwmac->dev, "Unsupported PHY mode %u\n", > > + plat->phy_interface); > > + return -EOPNOTSUPP; > > + } > > + > > + regmap_field_write(regmap_fields[GMAC1_SHUT], 0); > > + } else { > > + switch (plat->phy_interface) { > > + case PHY_INTERFACE_MODE_RGMII: > > + regmap_field_write(regmap_fields[GMAC0_USE_TXCLK], 0); > > + regmap_field_write(regmap_fields[GMAC0_USE_PWM01], 0); > > + break; > > same here. > > Andrew
On Tue, Aug 22, 2023 at 5:47 PM Keguang Zhang <keguang.zhang@gmail.com> wrote: > > On Mon, Aug 21, 2023 at 3:04 AM Andrew Lunn <andrew@lunn.ch> wrote: > > > > > +static int ls1b_dwmac_syscon_init(struct plat_stmmacenet_data *plat) > > > +{ > > > + struct ls1x_dwmac *dwmac = plat->bsp_priv; > > > + struct regmap_field **regmap_fields = dwmac->regmap_fields; > > > + > > > + if (plat->bus_id) { > > > + regmap_field_write(regmap_fields[GMAC1_USE_UART1], 1); > > > + regmap_field_write(regmap_fields[GMAC1_USE_UART0], 1); > > > + > > > + switch (plat->phy_interface) { > > > + case PHY_INTERFACE_MODE_RGMII: > > > + regmap_field_write(regmap_fields[GMAC1_USE_TXCLK], 0); > > > + regmap_field_write(regmap_fields[GMAC1_USE_PWM23], 0); > > > + break; > > > > What about the other three RGMII modes? Plain rgmii is pretty unusual, > > rgmii-id is the most used. > > > According to the LS1B datasheet, only RGMII and MII are supported. > And I can confirm that MII mode does work for LS1B. > Sorry! The RGMII mode does work for LS1B. > > > + case PHY_INTERFACE_MODE_MII: > > > + regmap_field_write(regmap_fields[GMAC1_USE_TXCLK], 1); > > > + regmap_field_write(regmap_fields[GMAC1_USE_PWM23], 1); > > > + break; > > > + default: > > > + dev_err(dwmac->dev, "Unsupported PHY mode %u\n", > > > + plat->phy_interface); > > > + return -EOPNOTSUPP; > > > + } > > > + > > > + regmap_field_write(regmap_fields[GMAC1_SHUT], 0); > > > + } else { > > > + switch (plat->phy_interface) { > > > + case PHY_INTERFACE_MODE_RGMII: > > > + regmap_field_write(regmap_fields[GMAC0_USE_TXCLK], 0); > > > + regmap_field_write(regmap_fields[GMAC0_USE_PWM01], 0); > > > + break; > > > > same here. > > > > Andrew > > > > -- > Best regards, > > Keguang Zhang
> > What about the other three RGMII modes? Plain rgmii is pretty unusual, > > rgmii-id is the most used. > > > According to the LS1B datasheet, only RGMII and MII are supported. > And I can confirm that MII mode does work for LS1B. What does your device tree look like? What are you setting phy-mode to in the rgmii case? As i said, "rgmii" is pretty unusual, you normally need "rgmii-id". Something in the system needs to add 2ns delays to the RGMII clock lines. Generally in device tree you pass phy-mode = "rgmii-id"; The MAC configures itself for RGMII, and passes PHY_INTERFACE_MODE_RGMII_ID to the PHY when it is attached. The PHY then inserts the delays. What is inserting the delays in your system? Andrew
> Sorry! The RGMII mode does work for LS1B.
and the question then is: How does it work?
Andrew
On Tue, Aug 22, 2023 at 11:20 PM Andrew Lunn <andrew@lunn.ch> wrote: > > > > What about the other three RGMII modes? Plain rgmii is pretty unusual, > > > rgmii-id is the most used. > > > > > According to the LS1B datasheet, only RGMII and MII are supported. > > And I can confirm that MII mode does work for LS1B. > > What does your device tree look like? What are you setting phy-mode to > in the rgmii case? As i said, "rgmii" is pretty unusual, you normally > need "rgmii-id". > > Something in the system needs to add 2ns delays to the RGMII clock > lines. Generally in device tree you pass phy-mode = "rgmii-id"; The > MAC configures itself for RGMII, and passes > PHY_INTERFACE_MODE_RGMII_ID to the PHY when it is attached. The PHY > then inserts the delays. > > What is inserting the delays in your system? > I understand the delay issue of RGMII. Just tried phy-mode = "rgmii-id", it still works. I will use PHY_INTERFACE_MODE_RGMII_ID instead. Thanks! > Andrew >
> I understand the delay issue of RGMII. > Just tried phy-mode = "rgmii-id", it still works. That indicates something is broken. Both "rgmii-id" and "rgmii" should not work, just one of them. What PHY driver are you using? Andrew
On Wed, Aug 23, 2023 at 11:46 AM Andrew Lunn <andrew@lunn.ch> wrote: > > > I understand the delay issue of RGMII. > > Just tried phy-mode = "rgmii-id", it still works. > > That indicates something is broken. Both "rgmii-id" and "rgmii" should > not work, just one of them. What PHY driver are you using? > I used generic PHY driver. Both "rgmii" and "rgmii-id" work with this driver. The PHY is RTL8211E. So I switch the PHY driver to Realtek driver. Now only "rgmii-id" works. Thanks! > Andrew > -- Best regards, Keguang Zhang
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 06c6871f8788..a2b9e289aa36 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -239,6 +239,17 @@ config DWMAC_INTEL_PLAT the stmmac device driver. This driver is used for the Intel Keem Bay SoC. +config DWMAC_LOONGSON1 + tristate "Loongson1 GMAC support" + default MACH_LOONGSON32 + depends on OF && (MACH_LOONGSON32 || COMPILE_TEST) + help + Support for ethernet controller on Loongson1 SoC. + + This selects Loongson1 SoC glue layer support for the stmmac + device driver. This driver is used for Loongson1-based boards + like Loongson LS1B/LS1C. + config DWMAC_TEGRA tristate "NVIDIA Tegra MGBE support" depends on ARCH_TEGRA || COMPILE_TEST diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index 5b57aee19267..80e598bd4255 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o +obj-$(CONFIG_DWMAC_LOONGSON1) += dwmac-loongson1.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c new file mode 100644 index 000000000000..5210b5e8ae47 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Loongson-1 DWMAC glue layer + * + * Copyright (C) 2011-2023 Keguang Zhang <keguang.zhang@gmail.com> + */ + +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "stmmac.h" +#include "stmmac_platform.h" + +/* Loongson-1 SYSCON Registers */ +#define LS1X_SYSCON0 (0x0) +#define LS1X_SYSCON1 (0x4) + +struct ls1x_dwmac_syscon { + const struct reg_field *reg_fields; + unsigned int nr_reg_fields; + int (*syscon_init)(struct plat_stmmacenet_data *plat); +}; + +struct ls1x_dwmac { + struct device *dev; + struct plat_stmmacenet_data *plat_dat; + const struct ls1x_dwmac_syscon *syscon; + struct regmap *regmap; + struct regmap_field *regmap_fields[]; +}; + +enum ls1b_dwmac_syscon_regfield { + GMAC1_USE_UART1, + GMAC1_USE_UART0, + GMAC1_SHUT, + GMAC0_SHUT, + GMAC1_USE_TXCLK, + GMAC0_USE_TXCLK, + GMAC1_USE_PWM23, + GMAC0_USE_PWM01, +}; + +enum ls1c_dwmac_syscon_regfield { + GMAC_SHUT, + PHY_INTF_SELI, +}; + +static const struct reg_field ls1b_dwmac_syscon_regfields[] = { + [GMAC1_USE_UART1] = REG_FIELD(LS1X_SYSCON0, 4, 4), + [GMAC1_USE_UART0] = REG_FIELD(LS1X_SYSCON0, 3, 3), + [GMAC1_SHUT] = REG_FIELD(LS1X_SYSCON1, 13, 13), + [GMAC0_SHUT] = REG_FIELD(LS1X_SYSCON1, 12, 12), + [GMAC1_USE_TXCLK] = REG_FIELD(LS1X_SYSCON1, 3, 3), + [GMAC0_USE_TXCLK] = REG_FIELD(LS1X_SYSCON1, 2, 2), + [GMAC1_USE_PWM23] = REG_FIELD(LS1X_SYSCON1, 1, 1), + [GMAC0_USE_PWM01] = REG_FIELD(LS1X_SYSCON1, 0, 0) +}; + +static const struct reg_field ls1c_dwmac_syscon_regfields[] = { + [GMAC_SHUT] = REG_FIELD(LS1X_SYSCON0, 6, 6), + [PHY_INTF_SELI] = REG_FIELD(LS1X_SYSCON1, 28, 30) +}; + +static int ls1b_dwmac_syscon_init(struct plat_stmmacenet_data *plat) +{ + struct ls1x_dwmac *dwmac = plat->bsp_priv; + struct regmap_field **regmap_fields = dwmac->regmap_fields; + + if (plat->bus_id) { + regmap_field_write(regmap_fields[GMAC1_USE_UART1], 1); + regmap_field_write(regmap_fields[GMAC1_USE_UART0], 1); + + switch (plat->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + regmap_field_write(regmap_fields[GMAC1_USE_TXCLK], 0); + regmap_field_write(regmap_fields[GMAC1_USE_PWM23], 0); + break; + case PHY_INTERFACE_MODE_MII: + regmap_field_write(regmap_fields[GMAC1_USE_TXCLK], 1); + regmap_field_write(regmap_fields[GMAC1_USE_PWM23], 1); + break; + default: + dev_err(dwmac->dev, "Unsupported PHY mode %u\n", + plat->phy_interface); + return -EOPNOTSUPP; + } + + regmap_field_write(regmap_fields[GMAC1_SHUT], 0); + } else { + switch (plat->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + regmap_field_write(regmap_fields[GMAC0_USE_TXCLK], 0); + regmap_field_write(regmap_fields[GMAC0_USE_PWM01], 0); + break; + case PHY_INTERFACE_MODE_MII: + regmap_field_write(regmap_fields[GMAC0_USE_TXCLK], 1); + regmap_field_write(regmap_fields[GMAC0_USE_PWM01], 1); + break; + default: + dev_err(dwmac->dev, "Unsupported PHY mode %u\n", + plat->phy_interface); + return -EOPNOTSUPP; + } + + regmap_field_write(regmap_fields[GMAC0_SHUT], 0); + } + + return 0; +} + +static int ls1c_dwmac_syscon_init(struct plat_stmmacenet_data *plat) +{ + struct ls1x_dwmac *dwmac = plat->bsp_priv; + struct regmap_field **regmap_fields = dwmac->regmap_fields; + + switch (plat->phy_interface) { + case PHY_INTERFACE_MODE_MII: + regmap_field_write(regmap_fields[PHY_INTF_SELI], 0); + break; + case PHY_INTERFACE_MODE_RMII: + regmap_field_write(regmap_fields[PHY_INTF_SELI], 4); + break; + default: + dev_err(dwmac->dev, "Unsupported PHY-mode %u\n", + plat->phy_interface); + return -EOPNOTSUPP; + } + + regmap_field_write(regmap_fields[GMAC_SHUT], 0); + + return 0; +} + +static const struct ls1x_dwmac_syscon ls1b_dwmac_syscon = { + .reg_fields = ls1b_dwmac_syscon_regfields, + .nr_reg_fields = ARRAY_SIZE(ls1b_dwmac_syscon_regfields), + .syscon_init = ls1b_dwmac_syscon_init, +}; + +static const struct ls1x_dwmac_syscon ls1c_dwmac_syscon = { + .reg_fields = ls1c_dwmac_syscon_regfields, + .nr_reg_fields = ARRAY_SIZE(ls1c_dwmac_syscon_regfields), + .syscon_init = ls1c_dwmac_syscon_init, +}; + +static int ls1x_dwmac_init(struct platform_device *pdev, void *priv) +{ + struct ls1x_dwmac *dwmac = priv; + int ret; + + ret = devm_regmap_field_bulk_alloc(dwmac->dev, dwmac->regmap, + dwmac->regmap_fields, + dwmac->syscon->reg_fields, + dwmac->syscon->nr_reg_fields); + if (ret) + return ret; + + if (dwmac->syscon->syscon_init) { + ret = dwmac->syscon->syscon_init(dwmac->plat_dat); + if (ret) + return ret; + } + + return 0; +} + +static const struct of_device_id ls1x_dwmac_syscon_match[] = { + { + .compatible = "loongson,ls1b-dwmac-syscon", + .data = &ls1b_dwmac_syscon, + }, + { + .compatible = "loongson,ls1c-dwmac-syscon", + .data = &ls1c_dwmac_syscon, + }, + { } +}; + +static int ls1x_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct device_node *syscon_np; + const struct of_device_id *match; + struct regmap *regmap; + struct ls1x_dwmac *dwmac; + const struct ls1x_dwmac_syscon *syscon; + size_t size; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + /* Probe syscon */ + syscon_np = + of_parse_phandle(pdev->dev.of_node, "loongson,dwmac-syscon", 0); + if (!syscon_np) { + dev_err(&pdev->dev, "missing loongson,dwmac-syscon property\n"); + return -ENODEV; + } + + match = of_match_node(ls1x_dwmac_syscon_match, syscon_np); + if (!match) { + dev_err(&pdev->dev, "no matching node found in dtb\n"); + of_node_put(syscon_np); + return -EINVAL; + } + syscon = (const struct ls1x_dwmac_syscon *)match->data; + + regmap = syscon_node_to_regmap(syscon_np); + of_node_put(syscon_np); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); + return ret; + } + + size = syscon->nr_reg_fields * sizeof(struct regmap_field *); + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac) + size, GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) { + dev_err(&pdev->dev, "dt configuration failed\n"); + return PTR_ERR(plat_dat); + } + + plat_dat->bsp_priv = dwmac; + plat_dat->init = ls1x_dwmac_init; + dwmac->dev = &pdev->dev; + dwmac->plat_dat = plat_dat; + dwmac->syscon = syscon; + dwmac->regmap = regmap; + + ret = stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); + if (ret) + goto err_remove_config_dt; + + return 0; + +err_remove_config_dt: + if (pdev->dev.of_node) + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; +} + +static const struct of_device_id ls1x_dwmac_match[] = { + { .compatible = "loongson,ls1b-dwmac" }, + { .compatible = "loongson,ls1c-dwmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, ls1x_dwmac_match); + +static struct platform_driver ls1x_dwmac_driver = { + .probe = ls1x_dwmac_probe, + .remove_new = stmmac_pltfr_remove, + .driver = { + .name = "loongson1-dwmac", + .of_match_table = ls1x_dwmac_match, + }, +}; +module_platform_driver(ls1x_dwmac_driver); + +MODULE_AUTHOR("Keguang Zhang <keguang.zhang@gmail.com>"); +MODULE_DESCRIPTION("Loongson1 DWMAC glue layer"); +MODULE_LICENSE("GPL");
This glue driver is created based on the arch-code implemented earlier with the platform-specific settings. Use syscon for SYSCON register access. Partialy based on the previous work by Serge Semin. Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> --- V1 -> V2: Fix the build errors due to CONFIG_OF being unset Change struct reg_field definitions to const Rename the syscon property to "loongson,dwmac-syscon" Add MII PHY mode for LS1C drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-loongson1.c | 273 ++++++++++++++++++ 3 files changed, 285 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c