diff mbox series

[v3,04/11] irqchip: mips-gic: Support multi-cluster in for_each_online_cpu_gic()

Message ID 20231031164927.371663-5-aleksandar.rikalo@syrmia.com (mailing list archive)
State Superseded
Headers show
Series MIPS: Support I6500 multi-cluster configuration | expand

Commit Message

Aleksandar Rikalo Oct. 31, 2023, 4:49 p.m. UTC
From: Paul Burton <paulburton@kernel.org>

Introduce support for multi-cluster GIC register access in
__gic_with_next_online_cpu(), and therefore in its user
for_each_online_cpu_gic(). We access registers in remote clusters
using the CM's GCR_CL_REDIRECT register, and so here we delegate
to mips_cm_lock_other() in order to configure this access.

With this done, users of gic_with_each_online_cpu() gain support
for multi-cluster with no further changes.

Signed-off-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
---
 drivers/irqchip/irq-mips-gic.c | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9e7182150b5c..317ccc2593d1 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -70,6 +70,20 @@  static int __gic_with_next_online_cpu(int prev)
 {
 	unsigned int cpu;
 
+	/*
+	 * Unlock access to the previous CPU's GIC local register block.
+	 *
+	 * Delegate to the CM locking code in the multi-cluster case, since
+	 * other clusters can only be accessed using GCR_CL_REDIRECT.
+	 *
+	 * In the single cluster case we don't need to do anything; the caller
+	 * is responsible for maintaining gic_lock & nothing should be
+	 * expecting any particular value of GIC_VL_OTHER so we can leave it
+	 * as-is.
+	 */
+	if ((prev != -1) && mips_cps_multicluster_cpus())
+		mips_cm_unlock_other();
+
 	/* Discover the next online CPU */
 	cpu = cpumask_next(prev, cpu_online_mask);
 
@@ -80,10 +94,16 @@  static int __gic_with_next_online_cpu(int prev)
 	/*
 	 * Lock access to the next CPU's GIC local register block.
 	 *
+	 * Delegate to the CM locking code in the multi-cluster case, since
+	 * other clusters can only be accessed using GCR_CL_REDIRECT.
+	 *
 	 * In the single cluster case we simply set GIC_VL_OTHER. The caller
 	 * holds gic_lock so nothing can clobber the value we write.
 	 */
-	write_gic_vl_other(mips_cm_vp_id(cpu));
+	if (mips_cps_multicluster_cpus())
+		mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
+	else
+		write_gic_vl_other(mips_cm_vp_id(cpu));
 
 	return cpu;
 }
@@ -105,6 +125,9 @@  static inline void __lockdep_assert_held(raw_spinlock_t *gic_lock)
  *
  * The caller must hold gic_lock throughout the loop, such that GIC_VL_OTHER
  * cannot be clobbered.
+ *
+ * Please note that if you start a loop this way, it must be completed to the
+ * end, otherwise, GIC local register block will remain locked.
  */
 #define for_each_online_cpu_gic(cpu, gic_lock)		\
 	for (__lockdep_assert_held(gic_lock),		\