From patchwork Tue Dec 12 16:34:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489633 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Tf9jdRrS" Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4939CE3; Tue, 12 Dec 2023 08:35:33 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 678F01BF20E; Tue, 12 Dec 2023 16:35:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398931; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s2HCa2+WQTWUMv9knwwE3fae1I7Q3ql8eVrDv9QUTaY=; b=Tf9jdRrSxXhoqOSFjwX/EXp1SxnnFjE15jIf+AR/W97xv7LdNXNXSiQKMPBtJBaI8jsM8u SOqyEZyudl2wAnWdTGS8im3yKZxp+EcuYsmEaTHSQoDPcQtO9bWp5CcsVK16xiTHfNJxf4 zK8EtY1PpfaouL3na3P0lEvbAVjnjLTMiYV5AY1DdBmYzc951qg3qT12Ck1zmx/613V4In oKEV3dQ3SZyMlhdXo1SxKXirl8s7fIPySmjxznNgRtwEoGdoHfdARgmJK/llgpF2DEg2Jw B996h7VjwNbbVaLSn4EzA0gIxTTZFkggUFXU5Sm4VJEPZQNfi0QNnbFHoml5cA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni Subject: [PATCH v5 09/22] MIPS: traps: Handle CPU with non standard vint offset Date: Tue, 12 Dec 2023 17:34:41 +0100 Message-ID: <20231212163459.1923041-10-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang Some BMIPS cpus has none standard start offset for vector interrupts. Handle those CPUs in vector size calculation and handler setup process. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ea59d321f713e..7e6e6df59e6d7 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -74,7 +74,6 @@ #include "access-helper.h" -#define MAX(a, b) ((a) >= (b) ? (a) : (b)) extern void check_wait(void); extern asmlinkage void rollback_handle_int(void); @@ -2005,6 +2004,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs) unsigned long ebase; EXPORT_SYMBOL_GPL(ebase); unsigned long exception_handlers[32]; +static unsigned long vi_vecbase; unsigned long vi_handlers[64]; void reserve_exception_space(phys_addr_t addr, unsigned long size) @@ -2074,7 +2074,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) handler = (unsigned long) addr; vi_handlers[n] = handler; - b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); + b = (unsigned char *)(vi_vecbase + n * VECTORSPACING); if (srs >= srssets) panic("Shadow register set %d not supported", srs); @@ -2370,20 +2370,33 @@ void __init trap_init(void) extern char except_vec3_generic; extern char except_vec4; extern char except_vec3_r4000; - unsigned long i, vec_size; + unsigned long i, vec_size, vi_vec_offset; phys_addr_t ebase_pa; check_wait(); + if (cpu_has_veic || cpu_has_vint) { + switch (current_cpu_type()) { + case CPU_BMIPS3300: + case CPU_BMIPS4380: + vi_vec_offset = 0x400; + break; + case CPU_BMIPS5000: + vi_vec_offset = 0x1000; + break; + default: + vi_vec_offset = 0x200; + break; + } + vec_size = vi_vec_offset + VECTORSPACING * 64; + } else { + vec_size = 0x400; + } + if (!cpu_has_mips_r2_r6) { ebase = CAC_BASE; - vec_size = 0x400; } else { - if (cpu_has_veic || cpu_has_vint) - vec_size = 0x200 + VECTORSPACING*64; - else - vec_size = PAGE_SIZE; - + vec_size = max(vec_size, PAGE_SIZE); ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); if (!ebase_pa) panic("%s: Failed to allocate %lu bytes align=0x%x\n", @@ -2450,6 +2463,7 @@ void __init trap_init(void) * Initialise interrupt handlers */ if (cpu_has_veic || cpu_has_vint) { + vi_vecbase = ebase + vi_vec_offset; int nvec = cpu_has_veic ? 64 : 8; for (i = 0; i < nvec; i++) set_vi_handler(i, NULL);