| Message ID | 20231218-mbly-reset-v1-3-b4688b916213@bootlin.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Add support for Mobileye EyeQ5 reset controller | expand |
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index d32da8fabe5a..b7da037ef324 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/interrupt-controller/mips-gic.h> +#include <dt-bindings/reset/mobileye,eyeq5-reset.h> /memreserve/ 0x40000000 0xc0000000; /* DDR32 */ @@ -76,6 +77,11 @@ olb: olb@e00000 { compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; reg = <0 0xe00000 0x0 0x400>; reg-io-width = <4>; + + reset: reset-controller { + compatible = "mobileye,eyeq5-reset"; + #reset-cells = <2>; + }; }; gic: interrupt-controller@140000 {
Add the devicetree node for the reset controller on the Mobileye EyeQ5 platform. It appears as a subnode to the OLB syscon as its registers are located in this shared register region. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)