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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id k8-20020a05600c1c8800b00418a6d62ad0sm9537339wms.34.2024.05.03.06.55.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 06:55:15 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , =?utf-8?q?=C3=81lvaro_Fern=C3=A1n?= =?utf-8?q?dez_Rojas?= , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Daniel_?= =?utf-8?q?Gonz=C3=A1lez_Cabanelas?= Subject: [PATCH 6/6] mips: bmips: dma: drop redundant boot_cpu_type in arch_dma_sync Date: Fri, 3 May 2024 15:54:07 +0200 Message-ID: <20240503135455.966-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240503135455.966-1-ansuelsmth@gmail.com> References: <20240503135455.966-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Drop redundant boot_cpu_type in arch_sync_dma_for_cpu_all. These needs to be parsed only once and we can make use of bmips_rac_flush_disable to disable RAC flush on unsupported CPU. Set this value in bmips_cpu_setup for unsupported CPU to skip this redundant check every time DMA needs to be synced. Signed-off-by: Christian Marangi --- arch/mips/bmips/dma.c | 5 ----- arch/mips/bmips/setup.c | 1 - arch/mips/include/asm/bmips.h | 1 + arch/mips/kernel/smp-bmips.c | 7 +++++++ 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c index 799cc3e12fc3..e9af34f82dcd 100644 --- a/arch/mips/bmips/dma.c +++ b/arch/mips/bmips/dma.c @@ -11,11 +11,6 @@ void arch_sync_dma_for_cpu_all(void) { u32 cfg; - if (boot_cpu_type() != CPU_BMIPS3300 && - boot_cpu_type() != CPU_BMIPS4350 && - boot_cpu_type() != CPU_BMIPS4380) - return; - if (unlikely(bmips_rac_flush_disable)) return; diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index bef84677248e..d27043b10405 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -40,7 +40,6 @@ * with "mips-cbr-reg" in the "cpus" node. */ void __iomem *bmips_cbr_addr; -extern bool bmips_rac_flush_disable; static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 3a1cdfddb987..4a48c8f1077e 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -82,6 +82,7 @@ extern char bmips_smp_int_vec[]; extern char bmips_smp_int_vec_end[]; extern void __iomem *bmips_cbr_addr; +extern bool bmips_rac_flush_disable; extern int bmips_smp_enabled; extern int bmips_cpu_offset; extern cpumask_t bmips_booted_mask; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 7bde6bbaa41f..63534af367c7 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -681,6 +681,13 @@ void bmips_cpu_setup(void) " or $8, $9\n" " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */ : : : "$8", "$9"); + + /* Disable RAC flush as not supported */ + bmips_rac_flush_disable = true; break; + + default: + /* Disable RAC flush as not supported */ + bmips_rac_flush_disable = true; } }