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Wed, 12 Jun 2024 05:53:34 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 10:53:29 +0100 Subject: [PATCH v2 1/4] MIPS: Introduce WAR_4KC_LLSC config option Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-llsc-v2-1-a42bd5562bdb@flygoat.com> References: <20240612-mips-llsc-v2-0-a42bd5562bdb@flygoat.com> In-Reply-To: <20240612-mips-llsc-v2-0-a42bd5562bdb@flygoat.com> To: Thomas Bogendoerfer Cc: Jonas Gorski , "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3467; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=9nYC1z3pwGvu5sxqw2LkoGhWr5mHdSDkIDT42XnAyFA=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTMAtl2hkK5Oz9Ub3t7d035+7b+ewJDo+M8Yd/e+79Uh Y5OWr+6o5SFQYyLQVZMkSVEQKlvQ+PFBdcfZP2BmcPKBDKEgYtTACYSsI/hf80GYQ37NzsMljju 9QkQ+2Xz79DV4iM7BGav5T/64bmqwxVGhs4kJ+v9O7zfHVMW5Zl9mP+Usul2wSmRZtdncAR6rb1 9lBcA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 WAR_4KC_LLSC is used to control workaround of 4KC LLSC issue that affects 4Kc up to version 0.9. Early ath25 chips are known to be affected. Signed-off-by: Jiaxun Yang --- v2: - Improve error message, taint kernel on error - Don't override cpu_has_llsc if WAR_4KC_LLSC is not selected, cpu-probe logic can handle it, there is no need to mess around ifdef as suggested in previous review comments as WAR_4KC_LLSC is gated by SOC_AR5312. --- arch/mips/Kconfig | 6 ++++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h | 6 ++---- arch/mips/kernel/cpu-probe.c | 9 +++++++++ 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1236ea122061..8ac467c1f9c8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -221,6 +221,7 @@ config ATH25 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_32BIT_KERNEL select SYS_HAS_EARLY_PRINTK + select WAR_4KC_LLSC if SOC_AR5312 help Support for Atheros AR231x and Atheros AR531x based boards @@ -2543,6 +2544,11 @@ config WAR_ICACHE_REFILLS config WAR_R10000_LLSC bool +# On 4Kc up to version 0.9 (PRID_REV < 1) there is a bug that may cause llsc +# sequences to deadlock. +config WAR_4KC_LLSC + bool + # 34K core erratum: "Problems Executing the TLBR Instruction" config WAR_MIPS34K_MISSED_ITLB bool diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index ecb9854cb432..84bb1931a8b4 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -247,6 +247,7 @@ #define PRID_REV_VR4122 0x0070 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 +#define PRID_REV_4KC_V1_0 0x0001 #define PRID_REV_34K_V1_0_2 0x0022 #define PRID_REV_LOONGSON1B 0x0020 #define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */ diff --git a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h index ec3604c44ef2..4cf3d1ffba1a 100644 --- a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h @@ -24,14 +24,12 @@ #define cpu_has_counter 1 #define cpu_has_ejtag 1 -#if !defined(CONFIG_SOC_AR5312) -# define cpu_has_llsc 1 -#else /* * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the * ll/sc instructions. */ -# define cpu_has_llsc 0 +#if !defined(WAR_4KC_LLSC) +# define cpu_has_llsc 1 #endif #define cpu_has_mips16 0 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index bda7f193baab..ff2905f59f2a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -152,6 +152,15 @@ static inline void check_errata(void) struct cpuinfo_mips *c = ¤t_cpu_data; switch (current_cpu_type()) { + case CPU_4KC: + if ((c->processor_id & PRID_REV_MASK) < PRID_REV_4KC_V1_0) { + c->options &= ~MIPS_CPU_LLSC; + if (cpu_has_llsc) { + pr_crit("CPU has LLSC erratum, but cpu_has_llsc is force enabled!\n"); + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + } + } + break; case CPU_34K: /* * Erratum "RPS May Cause Incorrect Instruction Execution"