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Sun, 16 Jun 2024 17:03:33 -0400 (EDT) From: Jiaxun Yang Date: Sun, 16 Jun 2024 22:03:06 +0100 Subject: [PATCH 02/10] MIPS: smp: Manage IPI interrupts as percpu_devid interrupts Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240616-b4-mips-ipi-improvements-v1-2-e332687f1692@flygoat.com> References: <20240616-b4-mips-ipi-improvements-v1-0-e332687f1692@flygoat.com> In-Reply-To: <20240616-b4-mips-ipi-improvements-v1-0-e332687f1692@flygoat.com> To: Thomas Bogendoerfer , Florian Fainelli , Broadcom internal kernel review list , Huacai Chen , Thomas Gleixner , Serge Semin , Paul Burton Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2703; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=wHsDiD50RoPx24lzv2aOKc2oWoxz6/3EkKTUFYyyMAw=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrT8YHn15v5VvZtXvrzFMZHxUdzxS4+urXDyun5xx9nOL Tx+Rcu5OkpZGMS4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BWAi9kqMDGdmdUh3JUbe2xpt wyP48MC0s8fPxLuEBiSGidxOlbpbqcrIMMNGfdZT2+WdpXN441a/mP9O5d82uyCLB9qLXlg1iqR LswAA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 IPI interrupts need to be enabled when a new CPU coming up. Manage them as percpu_devid interrupts and invoke enable/disable functions at appropriate time to perform enabling as required, similar to what RISC-V and Arm doing. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/ipi.h | 11 +++++++++++ arch/mips/kernel/smp.c | 26 ++++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/ipi.h b/arch/mips/include/asm/ipi.h index df7a0ac4227a..88b507339f51 100644 --- a/arch/mips/include/asm/ipi.h +++ b/arch/mips/include/asm/ipi.h @@ -29,6 +29,17 @@ int mips_smp_ipi_allocate(const struct cpumask *mask); * Return 0 on success. */ int mips_smp_ipi_free(const struct cpumask *mask); + +void mips_smp_ipi_enable(void); +void mips_smp_ipi_disable(void); +#else +static inline void mips_smp_ipi_enable(void) +{ +} + +static inline void mips_smp_ipi_disable(void) +{ +} #endif /* CONFIG_GENERIC_IRQ_IPI */ #endif /* CONFIG_SMP */ #endif diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index a6cf6444533e..710644d47106 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -186,6 +186,7 @@ irq_handler_t ipi_handlers[IPI_MAX] __read_mostly = { }; #ifdef CONFIG_GENERIC_IRQ_IPI +static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev); static int ipi_virqs[IPI_MAX] __ro_after_init; static struct irq_desc *ipi_desc[IPI_MAX] __read_mostly; @@ -225,13 +226,29 @@ void mips_smp_send_ipi_mask(const struct cpumask *mask, local_irq_restore(flags); } +void mips_smp_ipi_enable(void) +{ + int i; + + for (i = 0; i < IPI_MAX; i++) + enable_percpu_irq(ipi_virqs[i], IRQ_TYPE_NONE); +} + +void mips_smp_ipi_disable(void) +{ + int i; + + for (i = 0; i < IPI_MAX; i++) + disable_percpu_irq(ipi_virqs[i]); +} + static void smp_ipi_init_one(unsigned int virq, const char *name, irq_handler_t handler) { int ret; - irq_set_handler(virq, handle_percpu_irq); - ret = request_irq(virq, handler, IRQF_PERCPU, name, NULL); + irq_set_percpu_devid(virq); + ret = request_percpu_irq(virq, handler, "IPI", &ipi_dummy_dev); BUG_ON(ret); } @@ -343,6 +360,9 @@ static int __init mips_smp_ipi_init(void) return -ENODEV; } + /* Enable IPI for Boot CPU */ + mips_smp_ipi_enable(); + return 0; } early_initcall(mips_smp_ipi_init); @@ -383,6 +403,8 @@ asmlinkage void start_secondary(void) synchronise_count_slave(cpu); + mips_smp_ipi_enable(); + /* The CPU is running and counters synchronised, now mark it online */ set_cpu_online(cpu, true);