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Sun, 16 Jun 2024 17:03:50 -0400 (EDT) From: Jiaxun Yang Date: Sun, 16 Jun 2024 22:03:12 +0100 Subject: [PATCH 08/10] MIPS: GIC: Implement get_sw_int hook Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240616-b4-mips-ipi-improvements-v1-8-e332687f1692@flygoat.com> References: <20240616-b4-mips-ipi-improvements-v1-0-e332687f1692@flygoat.com> In-Reply-To: <20240616-b4-mips-ipi-improvements-v1-0-e332687f1692@flygoat.com> To: Thomas Bogendoerfer , Florian Fainelli , Broadcom internal kernel review list , Huacai Chen , Thomas Gleixner , Serge Semin , Paul Burton Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2476; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=M7QLa/e1lk3STQUI3hDEqiWEkdYQ/BEky6bbW4aA6gc=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrT8YHlBJ44nRxJXZH9fIXHq+H7B15Vrr9+4FXZH++ey0 JDUdXOudpSyMIhxMciKKbKECCj1bWi8uOD6g6w/MHNYmUCGMHBxCsBEXi9iZOi9evH8h1ThLeyW CyfvYG1cbm4xXaT5y0/WXM1j+/J6Njxi+KfvcDi0VXPavtgFa1053mnWLd47iWHHnWChq49U/Tz j1vECAA== X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 SW0 and SW1 interrupts are routed through GIC in EIC mode, implement get_sw_int hook for GIC and generic platform to create IRQ mapping for SW0 and SW1 in such mode. Signed-off-by: Jiaxun Yang --- arch/mips/generic/irq.c | 15 +++++++++++++++ arch/mips/include/asm/mips-gic.h | 10 ++++++++++ drivers/irqchip/irq-mips-gic.c | 15 +++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/arch/mips/generic/irq.c b/arch/mips/generic/irq.c index 933119262943..bc3599a76014 100644 --- a/arch/mips/generic/irq.c +++ b/arch/mips/generic/irq.c @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -59,3 +60,17 @@ unsigned int get_c0_compare_int(void) return mips_cpu_timer_irq; } + +int get_mips_sw_int(int hwint) +{ + int mips_sw_int_irq; + + if (mips_gic_present()) + mips_sw_int_irq = gic_get_sw_int(hwint); + else if (cpu_has_veic) + panic("Unimplemented!"); + else + mips_sw_int_irq = mips_cpu_get_sw_int(hwint); + + return mips_sw_int_irq; +} diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h index 084cac1c5ea2..83f0d04763bb 100644 --- a/arch/mips/include/asm/mips-gic.h +++ b/arch/mips/include/asm/mips-gic.h @@ -370,4 +370,14 @@ extern int gic_get_c0_perfcount_int(void); */ extern int gic_get_c0_fdc_int(void); +/** + * gic_get_sw_int() - Return software interrupt virq + * + * Determine the virq number to use for SWINT0 or SWINT1 interrupts, + * which may be routed via the GIC. + * + * Returns the virq number or a negative error number. + */ +extern int gic_get_sw_int(int hwirq); + #endif /* __MIPS_ASM_MIPS_CPS_H__ */ diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index eb58392f0e66..1fbd7de3796b 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -143,6 +143,21 @@ int gic_get_c0_fdc_int(void) GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); } +int gic_get_sw_int(int hwint) +{ + int local_irq; + + WARN_ON(hwint > 1); + + local_irq = GIC_LOCAL_INT_SWINT0 + hwint; + + if (!gic_local_irq_is_routable(local_irq)) + return MIPS_CPU_IRQ_BASE + hwint; + + return irq_create_mapping(gic_irq_domain, + GIC_LOCAL_TO_HWIRQ(local_irq)); +} + static void gic_handle_shared_int(bool chained) { unsigned int intr;