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AJvYcCXsgHz54TAEuFbYdLCNOEw8Go15pW+dIQ9m8TI/rm8lhM2HRhMlQvXfDOg5Qy9WL1psYspSf55Daj8sAAiudBQPWVWZFL+53kDNihOFQ0DMNiEMjrxMfpEqxSmcUlFROQ6An1AZo0g7Kw== X-Gm-Message-State: AOJu0Yz5HGNNIt/NCrv1Lrey0xkwSeRuKAV/I/UAAUIvtmOH31srhPRe FHcyxoIKB0dywzwH9ipCHpXQnfz8bF6ENi6Q7cMNQSfkdaGznT// X-Google-Smtp-Source: AGHT+IEjSYEEaX48FshcXj6CxYudxam3VGcC/uxrHOKGP4C6F0fyeI+wv5B6A6KMEDqcGR/KY0ulgw== X-Received: by 2002:a5d:42c9:0:b0:367:3282:a258 with SMTP id ffacd0b85a97d-367f717057emr704191f8f.18.1720686436374; Thu, 11 Jul 2024 01:27:16 -0700 (PDT) Received: from localhost.localdomain ([79.175.114.8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde84712sm7134283f8f.33.2024.07.11.01.27.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 01:27:15 -0700 (PDT) From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Aleksandar Rikalo , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang Subject: [PATCH v5 08/11] clocksource: mips-gic-timer: Enable counter when CPUs start Date: Thu, 11 Jul 2024 10:26:53 +0200 Message-Id: <20240711082656.1889440-9-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240711082656.1889440-1-arikalo@gmail.com> References: <20240711082656.1889440-1-arikalo@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Paul Burton In multi-cluster MIPS I6500 systems there is a GIC in each cluster, each with its own counter. When a cluster powers up the counter will be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. In single cluster systems, it has been fine to clear COUNTSTOP once in gic_clocksource_of_init() to start the counter. In multi-cluster systems, this will only have started the counter in the boot cluster, and any CPUs in other clusters will find their counter stopped which will break the GIC clock_event_device. Resolve this by having CPUs clear the COUNTSTOP bit when they come online, using the existing gic_starting_cpu() CPU hotplug callback. This will allow CPUs in secondary clusters to ensure that the cluster's GIC counter is running as expected. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daudé Tested-by: Serge Semin --- drivers/clocksource/mips-gic-timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index ebf308916fb1..4d7659c119e1 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -114,6 +114,9 @@ static void gic_update_frequency(void *data) static int gic_starting_cpu(unsigned int cpu) { + /* Ensure the GIC counter is running */ + clear_gic_config(GIC_CONFIG_COUNTSTOP); + gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); return 0; } @@ -284,9 +287,6 @@ static int __init gic_clocksource_of_init(struct device_node *node) pr_warn("Unable to register clock notifier\n"); } - /* And finally start the counter */ - clear_gic_config(GIC_CONFIG_COUNTSTOP); - /* * It's safe to use the MIPS GIC timer as a sched clock source only if * its ticks are stable, which is true on either the platforms with