| Message ID | 20240723-loongson-exttimer-v1-1-974bef8c2f88@flygoat.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 1cb6ab446424649f03c82334634360c2e3043684 |
| Headers | show |
| Series | MIPS: Loongson64: Set timer mode in cpu-probe | expand |
On Tue, Jul 23, 2024 at 05:15:44PM +0800, Jiaxun Yang wrote: > Loongson64 C and G processors have EXTIMER feature which > is conflicting with CP0 counter. > > Although the processor resets in EXTIMER disabled & INTIMER > enabled mode, which is compatible with MIPS CP0 compare, firmware > may attempt to enable EXTIMER and interfere CP0 compare. > > Set timer mode back to MIPS compatible mode to fix booting on > systems with such firmware before we have an actual driver for > EXTIMER. > > Cc: stable@vger.kernel.org > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > Please take this patch via fixes (or second 6.11 PR) tree so it can > reach stable faster. > > Thansks! > --- > arch/mips/kernel/cpu-probe.c | 4 ++++ > 1 file changed, 4 insertions(+) applied to mips-fixes. Thomas.
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index bda7f193baab..af7412549e6e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1724,12 +1724,16 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ + change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER, + LOONGSON_CONF6_INTIMER); break; case PRID_IMP_LOONGSON_64G: __cpu_name[cpu] = "ICT Loongson-3"; set_elf_platform(cpu, "loongson3a"); set_isa(c, MIPS_CPU_ISA_M64R2); decode_cpucfg(c); + change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER, + LOONGSON_CONF6_INTIMER); break; default: panic("Unknown Loongson Processor ID!");
Loongson64 C and G processors have EXTIMER feature which is conflicting with CP0 counter. Although the processor resets in EXTIMER disabled & INTIMER enabled mode, which is compatible with MIPS CP0 compare, firmware may attempt to enable EXTIMER and interfere CP0 compare. Set timer mode back to MIPS compatible mode to fix booting on systems with such firmware before we have an actual driver for EXTIMER. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- Please take this patch via fixes (or second 6.11 PR) tree so it can reach stable faster. Thansks! --- arch/mips/kernel/cpu-probe.c | 4 ++++ 1 file changed, 4 insertions(+) --- base-commit: dee7f101b64219f512bb2f842227bd04c14efe30 change-id: 20240723-loongson-exttimer-14b48e7ad5d6 Best regards,