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Sun, 8 Sep 2024 06:20:28 -0400 (EDT) From: Jiaxun Yang Date: Sun, 08 Sep 2024 11:20:19 +0100 Subject: [PATCH v5 08/10] MIPS: GIC: Implement get_sw_int hook Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240908-b4-mips-ipi-improvements-v5-8-be8617dd2e53@flygoat.com> References: <20240908-b4-mips-ipi-improvements-v5-0-be8617dd2e53@flygoat.com> In-Reply-To: <20240908-b4-mips-ipi-improvements-v5-0-be8617dd2e53@flygoat.com> To: Thomas Bogendoerfer , Florian Fainelli , Broadcom internal kernel review list , Huacai Chen , Thomas Gleixner , Serge Semin , Paul Burton Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2526; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=6W7V7EEEomFvzx7zP87p4zVKfdbX/dpvLnCVn/vqrn4=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrS7VQnX5rIHP/HczHez01DC89VRP+t/L7r1HlcnB5RYh CVEpDh1lLIwiHExyIopsoQIKPVtaLy44PqDrD8wc1iZQIYwcHEKwET4TjH8j9kuxrzN70YzS8vT zRIeS9fEBc2seHokwuqOSsHBWw//VzIyvFJjOLH57cFVTeaFZZOlRF6ZcyrH9N1dulB1zTeuZHN WFgA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 SW0 and SW1 interrupts are routed through GIC in EIC mode, implement get_sw_int hook for GIC and generic platform to create IRQ mapping for SW0 and SW1 in such mode. Tested-by: Serge Semin Signed-off-by: Jiaxun Yang --- arch/mips/generic/irq.c | 15 +++++++++++++++ arch/mips/include/asm/mips-gic.h | 10 ++++++++++ drivers/irqchip/irq-mips-gic.c | 15 +++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/arch/mips/generic/irq.c b/arch/mips/generic/irq.c index 933119262943..bc3599a76014 100644 --- a/arch/mips/generic/irq.c +++ b/arch/mips/generic/irq.c @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -59,3 +60,17 @@ unsigned int get_c0_compare_int(void) return mips_cpu_timer_irq; } + +int get_mips_sw_int(int hwint) +{ + int mips_sw_int_irq; + + if (mips_gic_present()) + mips_sw_int_irq = gic_get_sw_int(hwint); + else if (cpu_has_veic) + panic("Unimplemented!"); + else + mips_sw_int_irq = mips_cpu_get_sw_int(hwint); + + return mips_sw_int_irq; +} diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h index fd9da5e3beaa..3e9d1b252500 100644 --- a/arch/mips/include/asm/mips-gic.h +++ b/arch/mips/include/asm/mips-gic.h @@ -388,4 +388,14 @@ extern int gic_get_c0_perfcount_int(void); */ extern int gic_get_c0_fdc_int(void); +/** + * gic_get_sw_int() - Return software interrupt virq + * + * Determine the virq number to use for SWINT0 or SWINT1 interrupts, + * which may be routed via the GIC. + * + * Returns the virq number or a negative error number. + */ +extern int gic_get_sw_int(int hwirq); + #endif /* __MIPS_ASM_MIPS_CPS_H__ */ diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 4c36e10ee2d3..7fa567677c00 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -152,6 +152,21 @@ int gic_get_c0_fdc_int(void) GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); } +int gic_get_sw_int(int hwint) +{ + int local_irq; + + WARN_ON(hwint > 1); + + local_irq = GIC_LOCAL_INT_SWINT0 + hwint; + + if (!gic_local_irq_is_routable(local_irq)) + return MIPS_CPU_IRQ_BASE + hwint; + + return irq_create_mapping(gic_irq_domain, + GIC_LOCAL_TO_HWIRQ(local_irq)); +} + static void gic_handle_shared_int(bool chained) { unsigned int intr;