From patchwork Tue Oct 15 22:54:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13837362 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D74A1B3948 for ; Tue, 15 Oct 2024 22:54:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729032887; cv=none; b=KRTYZJ8/itfbgJDsAC6anm2f30PAr/ufgDRJg4Jc0QJU3/mmO6EuNdFTEWf/FpdZ3xKO+xHTrJY3b6pgIZww3/JZrbzkIiNczD2hOc8WsQQQ2LbUZAyguQdCBY8eMSfYTr2o7WBMw+x7mTpbMExVKiZvZeyRvpMbRAB3zjXPv04= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729032887; c=relaxed/simple; bh=28Zjchui2mSdO9738LkYgtGhtVQn7Su3e1XQElMPXKE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d2zVVKNmE8s0nNX4t54TAeJ6X7d3OX+ZXK7A4LkueyTrc8UEED6E8qrKkSUVbj+1PZSqwiS46WwOtipx7SzsCzxMMEnjTqrteVW/BuIVQ0mTYpMV1/xpBEg/BMOWVQHUkel6412LBzeq85bKV4Xp9v7pwhbp8cW3a+TXzYZJLO8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=oNVjaSMj; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="oNVjaSMj" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id D5BE12C038E; Wed, 16 Oct 2024 11:54:40 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1729032880; bh=SKVV3WFx27irMp2sL011rkHXlnDlzmjudKsVpWH3D7s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oNVjaSMjK7HynGw79H/JeCeAsUy3oAArk1CBM+3bG/55Lm1UBmmuPLe+j+gFZr04g MCtFcESNzqqS20vHQVbE56W/7a0dZTxU5/fppCdbmF/bf1he/EG91L6+e624MCYrxw l8tZQdcRuNj9+bA6H/gl/IbGjE0qbAYCNqJGqo1DDqvY+fZj0y+YfJ420+pTHnTNfo knG5oixH6R4QN5NkbB/U2F/+VUN6jC4VC3NRRsfLE6mUCPzx6NqB1/G2kYpu6rkafK U2DEbmOXrLurQFliH/NgpefGRm0eyglBRl6KEFIm7TxQ2c2BnreRsereFFScT585My 19xigSjs4Kz4g== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 16 Oct 2024 11:54:40 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 9D1A413EE9B; Wed, 16 Oct 2024 11:54:40 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 9AB4F28247E; Wed, 16 Oct 2024 11:54:40 +1300 (NZDT) From: Chris Packham To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, markus.stockhausen@gmx.de Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v5 2/3] mips: dts: realtek: Add SPI NAND controller Date: Wed, 16 Oct 2024 11:54:33 +1300 Message-ID: <20241015225434.3970360-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241015225434.3970360-1-chris.packham@alliedtelesis.co.nz> References: <20241015225434.3970360-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=ca1xrWDM c=1 sm=1 tr=0 ts=670ef2b0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=DAUX931o1VcA:10 a=8sy3EPFDi6gx0CG-VEIA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add the SPI-NAND controller on the RTL9300 family of devices. This supports serial/dual/quad data width and DMA for read/program operations. Signed-off-by: Chris Packham --- Notes: Changes in v4 & v5: - none Changes in v3: - drop wildcard rtl9300-snand compatible - drop clock-names Changes in v2: - Add clocks arch/mips/boot/dts/realtek/rtl930x.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi index f271940f82be..b01a40ec3064 100644 --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -32,6 +32,8 @@ lx_clk: clock-175mhz { }; &soc { + ranges = <0x0 0x18000000 0x20000>; + intc: interrupt-controller@3000 { compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; reg = <0x3000 0x18>, <0x3018 0x18>; @@ -59,6 +61,17 @@ timer0: timer@3200 { interrupts = <7>, <8>, <9>, <10>, <11>; clocks = <&lx_clk>; }; + + snand: spi@1a400 { + compatible = "realtek,rtl9301-snand"; + reg = <0x1a400 0x44>; + interrupt-parent = <&intc>; + interrupts = <19>; + clocks = <&lx_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; &uart0 {