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AJvYcCUF7UFHooxpaHx0VzbMGe14OKk4aIzMgmquS5RwTgHPtS1JmleIag5eI0Tp9nYuEX8NH56xZWqs07TO@vger.kernel.org, AJvYcCW9yDrzeSou8toq2XUNHBSqv1LfqFLLa2/agbClY+D0aTOq2uKIuvm88wDGvNJHSjDE5km78tBAtgxQCVCx@vger.kernel.org, AJvYcCWa6Tttuv3zKz8b2eNbzVXlfv++6ySWgI+GkJ6G/sfEtz2Z2FbPqNW9yeGtFLNGPozDboNojHCFDwb4kQ==@vger.kernel.org X-Gm-Message-State: AOJu0YyYgUNh100CCv4q2yZv1gNutrUUhW4TCTjeKcp/+YWWhItQG8XE bv1Nz6H+Oe75T0mqy8gwIKmLdhyaQ/day/0dbGjORLh9iX82zMaC X-Google-Smtp-Source: AGHT+IG5CeFXBy+88t4/mlcYBWdzsqbqzkUPO/IOnAI5iiWjhEbd5sESo8/SN+xxquLLJjOSBHxmhw== X-Received: by 2002:a17:906:da86:b0:a9a:49a8:f1fa with SMTP id a640c23a62f3a-a9de5db9e9bmr813270066b.23.1730138391023; Mon, 28 Oct 2024 10:59:51 -0700 (PDT) Received: from localhost.localdomain ([79.175.114.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b1dfbdfe2sm396990766b.36.2024.10.28.10.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2024 10:59:50 -0700 (PDT) From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Kondratiev , Gregory CLEMENT , Theo Lebrun , Arnd Bergmann , devicetree@vger.kernel.org, Djordje Todorovic , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Tiezhu Yang , Aleksandar Rikalo Subject: [PATCH v8 06/13] clocksource: mips-gic-timer: Enable counter when CPUs start Date: Mon, 28 Oct 2024 18:59:28 +0100 Message-Id: <20241028175935.51250-7-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241028175935.51250-1-arikalo@gmail.com> References: <20241028175935.51250-1-arikalo@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Paul Burton In multi-cluster MIPS I6500 systems there is a GIC in each cluster, each with its own counter. When a cluster powers up the counter will be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. In single cluster systems, it has been fine to clear COUNTSTOP once in gic_clocksource_of_init() to start the counter. In multi-cluster systems, this will only have started the counter in the boot cluster, and any CPUs in other clusters will find their counter stopped which will break the GIC clock_event_device. Resolve this by having CPUs clear the COUNTSTOP bit when they come online, using the existing gic_starting_cpu() CPU hotplug callback. This will allow CPUs in secondary clusters to ensure that the cluster's GIC counter is running as expected. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daudé Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- drivers/clocksource/mips-gic-timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index 7907b740497a..abb685a080a5 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -115,6 +115,9 @@ static void gic_update_frequency(void *data) static int gic_starting_cpu(unsigned int cpu) { + /* Ensure the GIC counter is running */ + clear_gic_config(GIC_CONFIG_COUNTSTOP); + gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); return 0; } @@ -288,9 +291,6 @@ static int __init gic_clocksource_of_init(struct device_node *node) pr_warn("Unable to register clock notifier\n"); } - /* And finally start the counter */ - clear_gic_config(GIC_CONFIG_COUNTSTOP); - /* * It's safe to use the MIPS GIC timer as a sched clock source only if * its ticks are stable, which is true on either the platforms with