From patchwork Fri Nov 15 15:29:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13876436 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A402E1D5CC2; Fri, 15 Nov 2024 15:30:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731684621; cv=none; b=cfhV/Z+N7GyrFo3lWPwzm1+WwJSTE66+EmSmAXCClDl7jR0ogOQfjU25DHtngoYGHZgOjTIVpa3ofQqxdl5K4MR8xqtfu2+Ua4AEoEyythrLeGXpvPywYFWoC3DSUtkKlBYkbLjOsdqBQPnu+ON/hOmWIEynlaLqwcZv4eRUk7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731684621; c=relaxed/simple; bh=daQgb2jNqZ0GK6GEn3Eju5Fx9agidHuO7KfcxhggVCE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OcKnYpXgZc3FyUf/VtcMKfsTCZ749W0/fPGA/U43EfuZv9j1Z24UsXy/Zgaq/D5i0MIpCedchtSjlDn1ZgmmBH9w03z9Stp+F1DBzjIdprop8yhvmh0wqV31sn+b8bAsqq/n9ifiyiIKYVnmAhW/QCW7HKltiYJr+BMCgG99a+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=iacbYRlF; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="iacbYRlF" Received: by mail.gandi.net (Postfix) with ESMTPSA id CD176FF80E; Fri, 15 Nov 2024 15:30:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731684611; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=buYxr7CUXzzx6XiXeAQUm7dN0AlNmhzNEVEstIlPdwg=; b=iacbYRlFP80sXwQPPMFx9wQmlO3bNzwKVLaBg1KKUkAgZJw+N8UXDgPYBD1oq8eWLiYuvg NH7b4PQoknlZuGAK5sZZN4EPwV8sZq8qJ5Tw1+iXhgbbmDqHjjpqH15KnhuSqmZM9Ho7SM qEbnLTaoyf6DXqjJKsiJAjnMcfq2VWgihEgMpLDzzK1WjyLdcX37l0mUzE6KZKNZcJivO0 NCMYmc5hg8qQ/rUsioOAEQu622onrXGrM7DQCBTLlMX71ImA88M5e2MOQBX6V0WbiA11hE puRwZpjcSm5373XA5/FYg4Pj35Cy9X3x5f2xHu82DKvLFpBYg+s4H2tUXDok1g== From: Gregory CLEMENT Date: Fri, 15 Nov 2024 16:29:56 +0100 Subject: [PATCH 3/5] MIPS: cm: Detect CM quirks from device tree Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241115-cluster-hci-broken-v1-3-00636800611d@bootlin.com> References: <20241115-cluster-hci-broken-v1-0-00636800611d@bootlin.com> In-Reply-To: <20241115-cluster-hci-broken-v1-0-00636800611d@bootlin.com> To: Aleksandar Rikalo , Thomas Bogendoerfer , Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Vladimir Kondratiev , =?utf-8?q?Th?= =?utf-8?q?=C3=A9o_Lebrun?= , Tawfik Bayouk , Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory CLEMENT X-Mailer: b4 0.14.2 X-GND-Sasl: gregory.clement@bootlin.com Some information that should be retrieved at runtime for the Coherence Manager can be either absent or wrong. This patch allows checking if some of this information is available from the device tree and updates the internal variable accordingly. For now, only the HCI broken-related property is being retrieved. Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/mips-cm.h | 22 ++++++++++++++++++++++ arch/mips/kernel/mips-cm.c | 16 ++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 1afa85db1fb37d1017fbe7d6b7a2b7d2470e8257..3bfe0633b57639bfb05b7692e4bb83ba7c0b2523 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -59,6 +59,16 @@ extern phys_addr_t mips_cm_l2sync_phys_base(void); */ extern int mips_cm_is64; +/* + * mips_cm_is_l2_hci_broken - determine if HCI is broken + * + * Some CM reports show that Hardware Cache Initialization is + * complete, but in reality it's not the case. They also incorrectly + * indicate that Hardware Cache Initialization is supported. This + * flags allows warning about this broken feature. + */ +extern bool mips_cm_is_l2_hci_broken; + /** * mips_cm_error_report - Report CM cache errors */ @@ -97,6 +107,18 @@ static inline bool mips_cm_present(void) #endif } +/** + * mips_cm_update_property - update property from the device tree + * + * Retrieve the properties from the device tree if a CM node exist and + * update the internal variable based on this. + */ +#ifdef CONFIG_MIPS_CM +extern void mips_cm_update_property(void); +#else +static void mips_cm_update_property(void) {} +#endif + /** * mips_cm_has_l2sync - determine whether an L2-only sync region is present * diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 9854bc2b6895d4db67d216586f65e4810661d29b..a2010b4d54c93175b63763bd5639c12e4583f58f 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -14,6 +15,7 @@ void __iomem *mips_gcr_base; void __iomem *mips_cm_l2sync_base; int mips_cm_is64; +bool mips_cm_is_l2_hci_broken; static char *cm2_tr[8] = { "mem", "gcr", "gic", "mmio", @@ -237,6 +239,20 @@ static void mips_cm_probe_l2sync(void) mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE); } +void mips_cm_update_property(void) +{ + struct device_node *cm_node; + + cm_node = of_find_compatible_node(of_root, NULL, "mti,mips-cm"); + if (!cm_node) + return; + if (of_property_read_bool(cm_node, "cm3-l2-config-hci-broken")) { + pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken"); + mips_cm_is_l2_hci_broken = true; + } + of_node_put(cm_node); +} + int mips_cm_probe(void) { phys_addr_t addr;