diff --git a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
index ba7ffc5b16a0..3d60e65836ed 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
@@ -18,6 +18,15 @@ description: |
   These SoCs have an XTAL from where the cpu clock is
   provided as well as derived clocks for the bus and the peripherals.
 
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
+
+  Reset related bits are defined in:
+  [2]: <include/dt-bindings/reset/mediatek,mtmips-sysc.h>.
+
 properties:
   compatible:
     items:
@@ -38,12 +47,14 @@ properties:
 
   '#clock-cells':
     description:
-      The first cell indicates the clock number.
+      The first cell indicates the clock number, see [1] for available
+      clocks.
     const: 1
 
   '#reset-cells':
     description:
-      The first cell indicates the reset bit within the register.
+      The first cell indicates the reset bit within the register, see
+      [2] for available resets.
     const: 1
 
 required:
@@ -56,6 +67,9 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+    #include <dt-bindings/reset/mediatek,mtmips-sysc.h>
+
     syscon@0 {
       compatible = "ralink,rt5350-sysc", "syscon";
       reg = <0x0 0x100>;
diff --git a/include/dt-bindings/clock/mediatek,mtmips-sysc.h b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
new file mode 100644
index 000000000000..a03335b0e077
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MTMIPS_H
+#define _DT_BINDINGS_CLK_MTMIPS_H
+
+/* Ralink RT-2880 clocks */
+
+#define RT2880_CLK_XTAL		0
+#define RT2880_CLK_CPU		1
+#define RT2880_CLK_BUS		2
+#define RT2880_CLK_TIMER	3
+#define RT2880_CLK_WATCHDOG	4
+#define RT2880_CLK_UART		5
+#define RT2880_CLK_I2C		6
+#define RT2880_CLK_UARTLITE	7
+#define RT2880_CLK_ETHERNET	8
+#define RT2880_CLK_WMAC		9
+
+/* Ralink RT-305X clocks */
+
+#define RT305X_CLK_XTAL		0
+#define RT305X_CLK_CPU		1
+#define RT305X_CLK_BUS		2
+#define RT305X_CLK_TIMER	3
+#define RT305X_CLK_WATCHDOG	4
+#define RT305X_CLK_UART		5
+#define RT305X_CLK_I2C		6
+#define RT305X_CLK_I2S		7
+#define RT305X_CLK_SPI1		8
+#define RT305X_CLK_SPI2		9
+#define RT305X_CLK_UARTLITE	10
+#define RT305X_CLK_ETHERNET	11
+#define RT305X_CLK_WMAC		12
+
+/* Ralink RT-3352 clocks */
+
+#define RT3352_CLK_XTAL		0
+#define RT3352_CLK_CPU		1
+#define RT3352_CLK_PERIPH	2
+#define RT3352_CLK_BUS		3
+#define RT3352_CLK_TIMER	4
+#define RT3352_CLK_WATCHDOG	5
+#define RT3352_CLK_UART		6
+#define RT3352_CLK_I2C		7
+#define RT3352_CLK_I2S		8
+#define RT3352_CLK_SPI1		9
+#define RT3352_CLK_SPI2		10
+#define RT3352_CLK_UARTLITE	11
+#define RT3352_CLK_ETHERNET	12
+#define RT3352_CLK_WMAC		13
+
+/* Ralink RT-3883 clocks */
+
+#define RT3883_CLK_XTAL		0
+#define RT3883_CLK_CPU		1
+#define RT3883_CLK_BUS		2
+#define RT3883_CLK_PERIPH	3
+#define RT3883_CLK_TIMER	4
+#define RT3883_CLK_WATCHDOG	5
+#define RT3883_CLK_UART		6
+#define RT3883_CLK_I2C		7
+#define RT3883_CLK_I2S		8
+#define RT3883_CLK_SPI1		9
+#define RT3883_CLK_SPI2		10
+#define RT3883_CLK_UARTLITE	11
+#define RT3883_CLK_ETHERNET	12
+#define RT3883_CLK_WMAC		13
+
+/* Ralink RT-5350 clocks */
+
+#define RT5350_CLK_XTAL		0
+#define RT5350_CLK_CPU		1
+#define RT5350_CLK_BUS		2
+#define RT5350_CLK_PERIPH	3
+#define RT5350_CLK_TIMER	4
+#define RT5350_CLK_WATCHDOG	5
+#define RT5350_CLK_UART		6
+#define RT5350_CLK_I2C		7
+#define RT5350_CLK_I2S		8
+#define RT5350_CLK_SPI1		9
+#define RT5350_CLK_SPI2		10
+#define RT5350_CLK_UARTLITE	11
+#define RT5350_CLK_ETHERNET	12
+#define RT5350_CLK_WMAC		13
+
+/* Ralink MT-7620 clocks */
+
+#define MT7620_CLK_XTAL		0
+#define MT7620_CLK_PLL		1
+#define MT7620_CLK_CPU		2
+#define MT7620_CLK_PERIPH	3
+#define MT7620_CLK_BUS		4
+#define MT7620_CLK_BBPPLL	5
+#define MT7620_CLK_SDHC		6
+#define MT7620_CLK_TIMER	7
+#define MT7620_CLK_WATCHDOG	8
+#define MT7620_CLK_UART		9
+#define MT7620_CLK_I2C		10
+#define MT7620_CLK_I2S		11
+#define MT7620_CLK_SPI1		12
+#define MT7620_CLK_SPI2		13
+#define MT7620_CLK_UARTLITE	14
+#define MT7620_CLK_MMC		15
+#define MT7620_CLK_WMAC		16
+
+/* Ralink MT-76X8 clocks */
+
+#define MT76X8_CLK_XTAL		0
+#define MT76X8_CLK_CPU		1
+#define MT76X8_CLK_BBPPLL	2
+#define MT76X8_CLK_PCMI2S	3
+#define MT76X8_CLK_PERIPH	4
+#define MT76X8_CLK_BUS		5
+#define MT76X8_CLK_SDHC		6
+#define MT76X8_CLK_TIMER	7
+#define MT76X8_CLK_WATCHDOG	8
+#define MT76X8_CLK_I2C		9
+#define MT76X8_CLK_I2S		10
+#define MT76X8_CLK_SPI1		11
+#define MT76X8_CLK_SPI2		12
+#define MT76X8_CLK_UART0	13
+#define MT76X8_CLK_UART1	14
+#define MT76X8_CLK_UART2	15
+#define MT76X8_CLK_MMC		16
+#define MT76X8_CLK_WMAC		17
+
+#endif /* _DT_BINDINGS_CLK_MTMIPS_H */
diff --git a/include/dt-bindings/reset/mediatek,mtmips-sysc.h b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
new file mode 100644
index 000000000000..1bc6024b1f22
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_RST_MTMIPS_H
+#define _DT_BINDINGS_RST_MTMIPS_H
+
+/* Ralink RT-2880 resets */
+
+#define RT2880_RST_SYS		0
+#define RT2880_RST_I2C		9
+#define RT2880_RST_FE		18
+
+/* Ralink RT-305X resets */
+
+#define RT305X_RST_SYS		0
+#define RT305X_RST_TIMER	8
+#define RT305X_RST_INTC		9
+#define RT305X_RST_MEMC		10
+#define RT305X_RST_PCM		11
+#define RT305X_RST_UART		12
+#define RT305X_RST_PIO		13
+#define RT305X_RST_DMA		14
+#define RT305X_RST_I2C		16
+#define RT305X_RST_I2S		17
+#define RT305X_RST_SPI		18
+#define RT305X_RST_UARTLITE	19
+#define RT305X_RST_WLAN		20
+#define RT305X_RST_FE		21
+#define RT305X_RST_OTG		22
+#define RT305X_RST_SW		23
+
+/* Ralink RT-3352 resets */
+
+#define RT3352_RST_SYS		0
+#define RT3352_RST_TIMER	8
+#define RT3352_RST_INTC		9
+#define RT3352_RST_MEMC		10
+#define RT3352_RST_PCM		11
+#define RT3352_RST_UART		12
+#define RT3352_RST_PIO		13
+#define RT3352_RST_DMA		14
+#define RT3352_RST_I2C		16
+#define RT3352_RST_I2S		17
+#define RT3352_RST_SPI		18
+#define RT3352_RST_UARTLITE	19
+#define RT3352_RST_WLAN		20
+#define RT3352_RST_FE		21
+#define RT3352_RST_UHST		22
+#define RT3352_RST_SW		23
+#define RT3352_RST_EPHY		24
+#define RT3352_RST_UDEV		25
+#define RT3352_RST_MIPS_CNT	28
+
+/* Ralink RT-3883 resets */
+
+#define RT3883_RST_SYS		0
+#define RT3883_RST_TIMER	8
+#define RT3883_RST_INTC		9
+#define RT3883_RST_MEMC		10
+#define RT3883_RST_PCM		11
+#define RT3883_RST_UART		12
+#define RT3883_RST_PIO		13
+#define RT3883_RST_DMA		14
+#define RT3883_RST_I2C		16
+#define RT3883_RST_I2S		17
+#define RT3883_RST_SPI		18
+#define RT3883_RST_UARTLITE	19
+#define RT3883_RST_WLAN		20
+#define RT3883_RST_FE		21
+#define RT3883_RST_UHST		22
+#define RT3883_RST_SW		23
+#define RT3883_RST_EPHY		24
+#define RT3883_RST_UDEV		25
+#define RT3883_RST_MIPS_CNT	28
+
+/* Ralink RT-5350 resets */
+
+#define RT5350_RST_SYS		0
+#define RT5350_RST_TIMER	8
+#define RT5350_RST_INTC		9
+#define RT5350_RST_MEMC		10
+#define RT5350_RST_PCM		11
+#define RT5350_RST_UART		12
+#define RT5350_RST_PIO		13
+#define RT5350_RST_DMA		14
+#define RT5350_RST_I2C		16
+#define RT5350_RST_I2S		17
+#define RT5350_RST_SPI		18
+#define RT5350_RST_UARTLITE	19
+#define RT5350_RST_WLAN		20
+#define RT5350_RST_FE		21
+#define RT5350_RST_UHST		22
+#define RT5350_RST_SW		23
+#define RT5350_RST_EPHY		24
+#define RT5350_RST_UDEV		25
+#define RT5350_RST_MIPS_CNT	28
+
+/* Ralink MT-7620 resets */
+
+#define MT7620_RST_SYS		0
+#define MT7620_RST_TIMER	8
+#define MT7620_RST_INTC		9
+#define MT7620_RST_MEMC		10
+#define MT7620_RST_PCM		11
+#define MT7620_RST_UART		12
+#define MT7620_RST_PIO		13
+#define MT7620_RST_DMA		14
+#define MT7620_RST_NAND		15
+#define MT7620_RST_I2C		16
+#define MT7620_RST_I2S		17
+#define MT7620_RST_SPI		18
+#define MT7620_RST_UARTLITE	19
+#define MT7620_RST_WLAN		20
+#define MT7620_RST_FE		21
+#define MT7620_RST_ESW		23
+#define MT7620_RST_EPHY		24
+#define MT7620_RST_UHST0	25
+#define MT7620_RST_PCIE0	26
+#define MT7620_RST_MIPS_CNT	28
+#define MT7620_RST_SDHC		30
+#define MT7620_RST_PPE		31
+
+/* Ralink MT-76X8 resets */
+
+#define MT76X8_RST_SYS		0
+#define MT76X8_RST_SPIS		3
+#define MT76X8_RST_WIFI		4
+#define MT76X8_RST_HIF		5
+#define MT76X8_RST_TIMER	8
+#define MT76X8_RST_INTC		9
+#define MT76X8_RST_MEMC		10
+#define MT76X8_RST_PCM		11
+#define MT76X8_RST_UART0	12
+#define MT76X8_RST_PIO		13
+#define MT76X8_RST_GDMA		14
+#define MT76X8_RST_I2C		16
+#define MT76X8_RST_I2S		17
+#define MT76X8_RST_SPI		18
+#define MT76X8_RST_UART1	19
+#define MT76X8_RST_UART2	20
+#define MT76X8_RST_UHST		22
+#define MT76X8_RST_ETH		23
+#define MT76X8_RST_EPHY		24
+#define MT76X8_RST_PCIE0	26
+#define MT76X8_RST_AUX_STCK	28
+#define MT76X8_RST_CRYPTO	29
+#define MT76X8_RST_SDXC		30
+#define MT76X8_RST_PWM		31
+
+#endif /* _DT_BINDINGS_RST_MTMIPS_H */
