| Message ID | 20250318214406.874733-1-arnd@kernel.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | mips: fix PCI_IOBASE definition | expand |
Hi Arnd, On Tue, Mar 18, 2025 at 10:44 PM Arnd Bergmann <arnd@kernel.org> wrote: > > From: Arnd Bergmann <arnd@arndb.de> > > After my previous patch, the ioport_map() function changed from > the lib/iomap.c version to the asm-generic/io.h version, which > requires a correct PCI_IOBASE definition. > > Unfortunately the types are also different, so add the correct > definition for ioport_map() in asm/io.h and change the machine > specific ones to have the correct type. > > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > --- > This is not pretty, but it seems to address the remaining problems. > I've applied it on top of my cross-architecture io.h cleanup that > has the other mips patch. > > Let me know if there are still any other concerns. > > > arch/mips/include/asm/io.h | 6 +++++- > arch/mips/include/asm/mach-loongson64/spaces.h | 5 +++-- > arch/mips/include/asm/mach-ralink/spaces.h | 2 +- > arch/mips/loongson64/init.c | 4 ++-- > 4 files changed, 11 insertions(+), 6 deletions(-) I have built and booted an image from your git tree 'master' branch on GNUBee PC2 board which is a MIPS mt7621 ralink based SoC: commit ac4e3b09c90480e17939f432da37a5328bad76ab (HEAD, arndtree/master, arndtree/asm-generic) Author: Arnd Bergmann <arnd@arndb.de> Date: Tue Mar 18 22:15:35 2025 +0100 mips: fix PCI_IOBASE definition After my previous patch, the ioport_map() function changed from the lib/iomap.c version to the asm-generic/io.h version, which requires a correct PCI_IOBASE definition. Unfortunately the types are also different, so add the correct definition for ioport_map() in asm/io.h and change the machine specific ones to have the correct type. Signed-off-by: Arnd Bergmann <arnd@arndb.de> It looks like nothing got broken regarding PCI enumeration on boot trace. I don't have real PCI cards with IO resources to test, but FWIW the enumeration is the same as from my stable 6.12 kernel boot. For completeness: [ 0.000000] Linux version 6.14.0-rc1+ (sergio@camaron) (mipsel-unknown-linux-gnu-gcc (GCC) 9.4.1 20211208, GNU ld (GNU Binutils) 2.37) #17 SMP Wed Mar 19 10:30:35 CET 2025 [ 0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3 [ 0.000000] printk: legacy bootconsole [early0] enabled [ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) [ 0.000000] MIPS: machine is GnuBee GB-PC2 ... [ 21.149742] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges: [ 21.163163] mt7621-pci 1e140000.pcie: MEM 0x0060000000..0x006fffffff -> 0x0060000000 [ 21.179519] mt7621-pci 1e140000.pcie: IO 0x001e160000..0x001e16ffff -> 0x0000000000 [ 21.524679] mt7621-pci 1e140000.pcie: PCIE0 enabled [ 21.534290] mt7621-pci 1e140000.pcie: PCIE1 enabled [ 21.544141] mt7621-pci 1e140000.pcie: PCIE2 enabled [ 21.554040] PCI coherence region base: 0x60000000, mask/settings: 0xf0000002 [ 21.568419] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00 [ 21.581116] pci_bus 0000:00: root bus resource [bus 00-ff] [ 21.592079] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] [ 21.605788] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 21.618237] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400 PCIe Root Port [ 21.632822] pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x7fffffff] [ 21.644670] pci 0000:00:00.0: BAR 1 [mem 0x00000000-0x0000ffff] [ 21.656445] pci 0000:00:00.0: PCI bridge to [bus 00] [ 21.666309] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff] [ 21.678361] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff] [ 21.691828] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff pref] [ 21.706279] pci 0000:00:00.0: supports D1 [ 21.714103] pci 0000:00:00.0: PME# supported from D0 D1 D3hot [ 21.726449] pci 0000:00:01.0: [0e8d:0801] type 01 class 0x060400 PCIe Root Port [ 21.740986] pci 0000:00:01.0: BAR 0 [mem 0x00000000-0x7fffffff] [ 21.752680] pci 0000:00:01.0: BAR 1 [mem 0x00000000-0x0000ffff] [ 21.764437] pci 0000:00:01.0: PCI bridge to [bus 00] [ 21.774292] pci 0000:00:01.0: bridge window [io 0x0000-0x0fff] [ 21.786381] pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff] [ 21.799858] pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff pref] [ 21.814286] pci 0000:00:01.0: supports D1 [ 21.822144] pci 0000:00:01.0: PME# supported from D0 D1 D3hot [ 21.834438] pci 0000:00:02.0: [0e8d:0801] type 01 class 0x060400 PCIe Root Port [ 21.849019] pci 0000:00:02.0: BAR 0 [mem 0x00000000-0x7fffffff] [ 21.860731] pci 0000:00:02.0: BAR 1 [mem 0x00000000-0x0000ffff] [ 21.872487] pci 0000:00:02.0: PCI bridge to [bus 00] [ 21.882335] pci 0000:00:02.0: bridge window [io 0x0000-0x0fff] [ 21.894437] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff] [ 21.907913] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff pref] [ 21.922343] pci 0000:00:02.0: supports D1 [ 21.930194] pci 0000:00:02.0: PME# supported from D0 D1 D3hot [ 21.943428] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 21.959309] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 21.975168] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 21.991373] pci 0000:01:00.0: [1b21:0611] type 00 class 0x010185 PCIe Legacy Endpoint [ 22.006936] pci 0000:01:00.0: BAR 0 [io 0x0000-0x0007] [ 22.017235] pci 0000:01:00.0: BAR 1 [io 0x0000-0x0003] [ 22.027589] pci 0000:01:00.0: BAR 2 [io 0x0000-0x0007] [ 22.037957] pci 0000:01:00.0: BAR 3 [io 0x0000-0x0003] [ 22.048325] pci 0000:01:00.0: BAR 4 [io 0x0000-0x000f] [ 22.058693] pci 0000:01:00.0: BAR 5 [mem 0x00000000-0x000001ff] [ 22.070611] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link) [ 22.114603] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [ 22.124936] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 [ 22.138347] pci 0000:02:00.0: [1b21:0611] type 00 class 0x010185 PCIe Legacy Endpoint [ 22.153917] pci 0000:02:00.0: BAR 0 [io 0x0000-0x0007] [ 22.164212] pci 0000:02:00.0: BAR 1 [io 0x0000-0x0003] [ 22.174587] pci 0000:02:00.0: BAR 2 [io 0x0000-0x0007] [ 22.184948] pci 0000:02:00.0: BAR 3 [io 0x0000-0x0003] [ 22.195311] pci 0000:02:00.0: BAR 4 [io 0x0000-0x000f] [ 22.205685] pci 0000:02:00.0: BAR 5 [mem 0x00000000-0x000001ff] [ 22.217590] pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link) [ 22.264617] pci 0000:00:01.0: PCI bridge to [bus 02-ff] [ 22.274959] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02 [ 22.288402] pci 0000:03:00.0: [1b21:0611] type 00 class 0x010185 PCIe Legacy Endpoint [ 22.303981] pci 0000:03:00.0: BAR 0 [io 0x0000-0x0007] [ 22.314270] pci 0000:03:00.0: BAR 1 [io 0x0000-0x0003] [ 22.324651] pci 0000:03:00.0: BAR 2 [io 0x0000-0x0007] [ 22.335005] pci 0000:03:00.0: BAR 3 [io 0x0000-0x0003] [ 22.345372] pci 0000:03:00.0: BAR 4 [io 0x0000-0x000f] [ 22.355745] pci 0000:03:00.0: BAR 5 [mem 0x00000000-0x000001ff] [ 22.367654] pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:02.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link) [ 22.414605] pci 0000:00:02.0: PCI bridge to [bus 03-ff] [ 22.424945] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03 [ 22.438133] pci 0000:00:00.0: BAR 0 [mem size 0x80000000]: can't assign; no space [ 22.452906] pci 0000:00:00.0: BAR 0 [mem size 0x80000000]: failed to assign [ 22.466731] pci 0000:00:01.0: BAR 0 [mem size 0x80000000]: can't assign; no space [ 22.481599] pci 0000:00:01.0: BAR 0 [mem size 0x80000000]: failed to assign [ 22.495413] pci 0000:00:02.0: BAR 0 [mem size 0x80000000]: can't assign; no space [ 22.510272] pci 0000:00:02.0: BAR 0 [mem size 0x80000000]: failed to assign [ 22.524106] pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff]: assigned [ 22.538973] pci 0000:00:00.0: bridge window [mem 0x60100000-0x601fffff pref]: assigned [ 22.554690] pci 0000:00:01.0: bridge window [mem 0x60200000-0x602fffff]: assigned [ 22.569548] pci 0000:00:01.0: bridge window [mem 0x60300000-0x603fffff pref]: assigned [ 22.585270] pci 0000:00:02.0: bridge window [mem 0x60400000-0x604fffff]: assigned [ 22.600145] pci 0000:00:02.0: bridge window [mem 0x60500000-0x605fffff pref]: assigned [ 22.615856] pci 0000:00:00.0: BAR 1 [mem 0x60600000-0x6060ffff]: assigned [ 22.629342] pci 0000:00:01.0: BAR 1 [mem 0x60610000-0x6061ffff]: assigned [ 22.642816] pci 0000:00:02.0: BAR 1 [mem 0x60620000-0x6062ffff]: assigned [ 22.656306] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]: assigned [ 22.669776] pci 0000:00:01.0: bridge window [io 0x1000-0x1fff]: assigned [ 22.683249] pci 0000:00:02.0: bridge window [io 0x2000-0x2fff]: assigned [ 22.696739] pci 0000:01:00.0: BAR 5 [mem 0x60000000-0x600001ff]: assigned [ 22.710216] pci 0000:01:00.0: BAR 4 [io 0x0000-0x000f]: assigned [ 22.722313] pci 0000:01:00.0: BAR 0 [io 0x0010-0x0017]: assigned [ 22.734402] pci 0000:01:00.0: BAR 2 [io 0x0018-0x001f]: assigned [ 22.746496] pci 0000:01:00.0: BAR 1 [io 0x0020-0x0023]: assigned [ 22.758594] pci 0000:01:00.0: BAR 3 [io 0x0024-0x0027]: assigned [ 22.770695] pci 0000:00:00.0: PCI bridge to [bus 01] [ 22.780547] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff] [ 22.792631] pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff] [ 22.806106] pci 0000:00:00.0: bridge window [mem 0x60100000-0x601fffff pref] [ 22.820461] pci 0000:02:00.0: BAR 5 [mem 0x60200000-0x602001ff]: assigned [ 22.833940] pci 0000:02:00.0: BAR 4 [io 0x1000-0x100f]: assigned [ 22.846037] pci 0000:02:00.0: BAR 0 [io 0x1010-0x1017]: assigned [ 22.858127] pci 0000:02:00.0: BAR 2 [io 0x1018-0x101f]: assigned [ 22.870223] pci 0000:02:00.0: BAR 1 [io 0x1020-0x1023]: assigned [ 22.882319] pci 0000:02:00.0: BAR 3 [io 0x1024-0x1027]: assigned [ 22.894423] pci 0000:00:01.0: PCI bridge to [bus 02] [ 22.904263] pci 0000:00:01.0: bridge window [io 0x1000-0x1fff] [ 22.916359] pci 0000:00:01.0: bridge window [mem 0x60200000-0x602fffff] [ 22.929833] pci 0000:00:01.0: bridge window [mem 0x60300000-0x603fffff pref] [ 22.944185] pci 0000:03:00.0: BAR 5 [mem 0x60400000-0x604001ff]: assigned [ 22.957663] pci 0000:03:00.0: BAR 4 [io 0x2000-0x200f]: assigned [ 22.969756] pci 0000:03:00.0: BAR 0 [io 0x2010-0x2017]: assigned [ 22.981859] pci 0000:03:00.0: BAR 2 [io 0x2018-0x201f]: assigned [ 22.993949] pci 0000:03:00.0: BAR 1 [io 0x2020-0x2023]: assigned [ 23.006046] pci 0000:03:00.0: BAR 3 [io 0x2024-0x2027]: assigned [ 23.018150] pci 0000:00:02.0: PCI bridge to [bus 03] [ 23.027983] pci 0000:00:02.0: bridge window [io 0x2000-0x2fff] [ 23.040087] pci 0000:00:02.0: bridge window [mem 0x60400000-0x604fffff] [ 23.053557] pci 0000:00:02.0: bridge window [mem 0x60500000-0x605fffff pref] [ 23.067900] pci_bus 0000:00: Some PCI device resources are unassigned, try booting with pci=realloc [ 23.085874] pci_bus 0000:00: resource 4 [mem 0x60000000-0x6fffffff] [ 23.098318] pci_bus 0000:00: resource 5 [io 0x0000-0xffff] [ 23.109370] pci_bus 0000:01: resource 0 [io 0x0000-0x0fff] [ 23.120434] pci_bus 0000:01: resource 1 [mem 0x60000000-0x600fffff] [ 23.132870] pci_bus 0000:01: resource 2 [mem 0x60100000-0x601fffff pref] [ 23.146184] pci_bus 0000:02: resource 0 [io 0x1000-0x1fff] [ 23.157242] pci_bus 0000:02: resource 1 [mem 0x60200000-0x602fffff] [ 23.169680] pci_bus 0000:02: resource 2 [mem 0x60300000-0x603fffff pref] [ 23.182983] pci_bus 0000:03: resource 0 [io 0x2000-0x2fff] [ 23.194041] pci_bus 0000:03: resource 1 [mem 0x60400000-0x604fffff] [ 23.206488] pci_bus 0000:03: resource 2 [mem 0x60500000-0x605fffff pref] ... So, feel free to add my: Tested-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> # Mt7621 Ralink Let me know if you want me to check anything else. Best regards, Sergio Paracuellos
On Wed, Mar 19, 2025, at 10:43, Sergio Paracuellos wrote: > Hi Arnd, > > On Tue, Mar 18, 2025 at 10:44 PM Arnd Bergmann <arnd@kernel.org> wrote: > > It looks like nothing got broken regarding PCI enumeration on boot > trace. I don't have real PCI cards with IO resources to test, but FWIW > the enumeration is the same as from my stable 6.12 kernel boot. > Thanks a lot for testing! Arnd
On Wed, Mar 19, 2025 at 11:07:46AM +0100, Arnd Bergmann wrote: > On Wed, Mar 19, 2025, at 10:43, Sergio Paracuellos wrote: > > Hi Arnd, > > > > On Tue, Mar 18, 2025 at 10:44 PM Arnd Bergmann <arnd@kernel.org> wrote: > > > > It looks like nothing got broken regarding PCI enumeration on boot > > trace. I don't have real PCI cards with IO resources to test, but FWIW > > the enumeration is the same as from my stable 6.12 kernel boot. > > > > Thanks a lot for testing! are you taking it together with your other io,h cleanups ? Thomas.
On Wed, Mar 19, 2025, at 11:38, Thomas Bogendoerfer wrote: > On Wed, Mar 19, 2025 at 11:07:46AM +0100, Arnd Bergmann wrote: >> On Wed, Mar 19, 2025, at 10:43, Sergio Paracuellos wrote: >> > Hi Arnd, >> > >> > On Tue, Mar 18, 2025 at 10:44 PM Arnd Bergmann <arnd@kernel.org> wrote: >> > >> > It looks like nothing got broken regarding PCI enumeration on boot >> > trace. I don't have real PCI cards with IO resources to test, but FWIW >> > the enumeration is the same as from my stable 6.12 kernel boot. >> > >> >> Thanks a lot for testing! > > are you taking it together with your other io,h cleanups ? Yes, I've pushed it out into my asm-generic branch. Arnd
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 1fe56d1870a6..78c6573f91f2 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -544,12 +544,16 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); void __ioread64_copy(void *to, const void __iomem *from, size_t count); -#ifdef CONFIG_PCI_DRIVERS_LEGACY +#if defined(CONFIG_PCI) && defined(CONFIG_PCI_DRIVERS_LEGACY) struct pci_dev; void pci_iounmap(struct pci_dev *dev, void __iomem *addr); #define pci_iounmap pci_iounmap #endif +#ifndef PCI_IOBASE +#define PCI_IOBASE ((void __iomem *)mips_io_port_base) +#endif + #include <asm-generic/io.h> static inline void *isa_bus_to_virt(unsigned long address) diff --git a/arch/mips/include/asm/mach-loongson64/spaces.h b/arch/mips/include/asm/mach-loongson64/spaces.h index ce04e998a37b..dbd26db5f2c5 100644 --- a/arch/mips/include/asm/mach-loongson64/spaces.h +++ b/arch/mips/include/asm/mach-loongson64/spaces.h @@ -7,9 +7,10 @@ #endif /* CONFIG_64BIT */ /* Skip 128k to trap NULL pointer dereferences */ -#define PCI_IOBASE _AC(0xc000000000000000 + SZ_128K, UL) +#define PCI_PORT_BASE _AC(0xc000000000000000 + SZ_128K, UL) +#define PCI_IOBASE (void __iomem *)PCI_PORT_BASE #define PCI_IOSIZE SZ_16M -#define MAP_BASE (PCI_IOBASE + PCI_IOSIZE) +#define MAP_BASE (PCI_PORT_BASE + PCI_IOSIZE) #define IO_SPACE_LIMIT (PCI_IOSIZE - 1) diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h index a9f0570d0f04..a63d106c89c6 100644 --- a/arch/mips/include/asm/mach-ralink/spaces.h +++ b/arch/mips/include/asm/mach-ralink/spaces.h @@ -2,7 +2,7 @@ #ifndef __ASM_MACH_RALINK_SPACES_H_ #define __ASM_MACH_RALINK_SPACES_H_ -#define PCI_IOBASE mips_io_port_base +#define PCI_IOBASE (void __iomem *)mips_io_port_base #define PCI_IOSIZE SZ_64K #define IO_SPACE_LIMIT (PCI_IOSIZE - 1) diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c index a35dd7311795..b9f90f33fc9a 100644 --- a/arch/mips/loongson64/init.c +++ b/arch/mips/loongson64/init.c @@ -128,7 +128,7 @@ void __init prom_init(void) } /* init base address of io space */ - set_io_port_base(PCI_IOBASE); + set_io_port_base((unsigned long)PCI_IOBASE); if (loongson_sysconf.early_config) loongson_sysconf.early_config(); @@ -178,7 +178,7 @@ static int __init add_legacy_isa_io(struct fwnode_handle *fwnode, resource_size_ return -EINVAL; } - vaddr = PCI_IOBASE + range->io_start; + vaddr = (unsigned long)PCI_IOBASE + range->io_start; vmap_page_range(vaddr, vaddr + size, hw_start, pgprot_device(PAGE_KERNEL));