| Message ID | 20250321134633.2155141-3-cjd@cjdns.fr (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add EcoNet EN751221 MIPS platform support | expand |
On Fri, 21 Mar 2025 13:46:27 +0000, Caleb James DeLisle wrote: > Document the device tree binding for the interrupt controller in the > EcoNet EN751221 MIPS SoC. > > Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> > --- > If anyone is aware of a standard name for this "shadow interrupt" pattern, > please let me know and I will re-send with updated naming. > --- > .../econet,en751221-intc.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.example.dtb: interrupt-controller@1fb40000: 'interrupt-parent' is a required property from schema $id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250321134633.2155141-3-cjd@cjdns.fr The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 21/03/2025 16:52, Rob Herring (Arm) wrote: > On Fri, 21 Mar 2025 13:46:27 +0000, Caleb James DeLisle wrote: >> Document the device tree binding for the interrupt controller in the >> EcoNet EN751221 MIPS SoC. >> >> Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> >> --- >> If anyone is aware of a standard name for this "shadow interrupt" pattern, >> please let me know and I will re-send with updated naming. >> --- >> .../econet,en751221-intc.yaml | 77 +++++++++++++++++++ >> 1 file changed, 77 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml >> > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.example.dtb: interrupt-controller@1fb40000: 'interrupt-parent' is a required property > from schema $id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# > Reproduced and fixed, thank you. In the interest of limiting mailing list noise, I plan to send a v2 sometime around Monday, ideally to aggregate a few more reviews in the process. Thanks, Caleb
On Fri, Mar 21, 2025 at 01:46:27PM +0000, Caleb James DeLisle wrote: > Document the device tree binding for the interrupt controller in the > EcoNet EN751221 MIPS SoC. > > Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> > --- > If anyone is aware of a standard name for this "shadow interrupt" pattern, > please let me know and I will re-send with updated naming. > --- > .../econet,en751221-intc.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml > new file mode 100644 > index 000000000000..1b0f262c9630 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: EcoNet EN751221 Interrupt Controller > + > +maintainers: > + - Caleb James DeLisle <cjd@cjdns.fr> > + > +description: | Don't need '|' if no formatting. > + The EcoNet EN751221 Interrupt Controller is a simple interrupt controller > + designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can > + be routed to either VPE but not both, so to support per-CPU interrupts, a > + secondary IRQ number is allocated to control masking/unmasking on VPE#1. For > + lack of a better term we call these "shadow interrupts". The assignment of > + shadow interrupts is defined by the SoC integrator when wiring the interrupt > + lines, so they are configurable in the device tree. > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + const: econet,en751221-intc > + > + reg: > + maxItems: 1 > + > + "#interrupt-cells": > + const: 1 > + > + interrupt-controller: true > + > + interrupts: > + maxItems: 1 > + description: Interrupt line connecting this controller to its parent. > + > + econet,shadow-interrupts: > + $ref: /schemas/types.yaml#/definitions/uint32-array Looks like uint32-matrix to me as it pairs of u32's. > + description: | > + An array of interrupt number pairs where each pair represents a shadow > + interrupt relationship. The first number in each pair is the primary IRQ, > + and the second is its shadow IRQ used for VPE#1 control. For example, > + <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but > + when VPE#1 requests IRQ 8, it will use manipulate the IRQ 3 mask bit. > + maxItems: 40 > + items: > + minimum: 0 > + maximum: 40 Then this would be: minItems: 1 maxItems: 40 items: items: - description: primary IRQ - description: shadow IRQ (Feel free to expand the descriptions) > + > +required: > + - compatible > + - reg > + - interrupt-controller > + - "#interrupt-cells" > + - interrupt-parent Generally, interrupt-parent is never required. It can be in a parent node for example. > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + intc: interrupt-controller@1fb40000 { Drop unused labels (intc). > + compatible = "econet,en751221-intc"; > + reg = <0x1fb40000 0x100>; > + > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interrupt-parent = <&cpuintc>; > + interrupts = <2>; > + > + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; > + }; > +... > -- > 2.30.2 >
On 21/03/2025 22:17, Rob Herring wrote: > On Fri, Mar 21, 2025 at 01:46:27PM +0000, Caleb James DeLisle wrote: >> Document the device tree binding for the interrupt controller in the >> EcoNet EN751221 MIPS SoC. >> >> Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> >> --- >> If anyone is aware of a standard name for this "shadow interrupt" pattern, >> please let me know and I will re-send with updated naming. >> --- >> .../econet,en751221-intc.yaml | 77 +++++++++++++++++++ >> 1 file changed, 77 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml >> new file mode 100644 >> index 000000000000..1b0f262c9630 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml >> @@ -0,0 +1,77 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: EcoNet EN751221 Interrupt Controller >> + >> +maintainers: >> + - Caleb James DeLisle <cjd@cjdns.fr> >> + >> +description: | > Don't need '|' if no formatting. Got it, thanks. > >> + The EcoNet EN751221 Interrupt Controller is a simple interrupt controller >> + designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can >> + be routed to either VPE but not both, so to support per-CPU interrupts, a >> + secondary IRQ number is allocated to control masking/unmasking on VPE#1. For >> + lack of a better term we call these "shadow interrupts". The assignment of >> + shadow interrupts is defined by the SoC integrator when wiring the interrupt >> + lines, so they are configurable in the device tree. >> + >> +allOf: >> + - $ref: /schemas/interrupt-controller.yaml# >> + >> +properties: >> + compatible: >> + const: econet,en751221-intc >> + >> + reg: >> + maxItems: 1 >> + >> + "#interrupt-cells": >> + const: 1 >> + >> + interrupt-controller: true >> + >> + interrupts: >> + maxItems: 1 >> + description: Interrupt line connecting this controller to its parent. >> + >> + econet,shadow-interrupts: >> + $ref: /schemas/types.yaml#/definitions/uint32-array > Looks like uint32-matrix to me as it pairs of u32's. Thanks for the pointer, will update. > >> + description: | >> + An array of interrupt number pairs where each pair represents a shadow >> + interrupt relationship. The first number in each pair is the primary IRQ, >> + and the second is its shadow IRQ used for VPE#1 control. For example, >> + <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but >> + when VPE#1 requests IRQ 8, it will use manipulate the IRQ 3 mask bit. >> + maxItems: 40 >> + items: >> + minimum: 0 >> + maximum: 40 > Then this would be: > > minItems: 1 > maxItems: 40 > items: > items: > - description: primary IRQ > - description: shadow IRQ > > (Feel free to expand the descriptions) Yes, much nicer. > >> + >> +required: >> + - compatible >> + - reg >> + - interrupt-controller >> + - "#interrupt-cells" >> + - interrupt-parent > Generally, interrupt-parent is never required. It can be in a parent > node for example. Removed, thanks. > >> + - interrupts >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + intc: interrupt-controller@1fb40000 { > Drop unused labels (intc). Ok. Thank you very much for your time, hope to see you soon in v2. Thanks, Caleb > >> + compatible = "econet,en751221-intc"; >> + reg = <0x1fb40000 0x100>; >> + >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + >> + interrupt-parent = <&cpuintc>; >> + interrupts = <2>; >> + >> + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; >> + }; >> +... >> -- >> 2.30.2 >>
diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml new file mode 100644 index 000000000000..1b0f262c9630 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet EN751221 Interrupt Controller + +maintainers: + - Caleb James DeLisle <cjd@cjdns.fr> + +description: | + The EcoNet EN751221 Interrupt Controller is a simple interrupt controller + designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can + be routed to either VPE but not both, so to support per-CPU interrupts, a + secondary IRQ number is allocated to control masking/unmasking on VPE#1. For + lack of a better term we call these "shadow interrupts". The assignment of + shadow interrupts is defined by the SoC integrator when wiring the interrupt + lines, so they are configurable in the device tree. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: econet,en751221-intc + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Interrupt line connecting this controller to its parent. + + econet,shadow-interrupts: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of interrupt number pairs where each pair represents a shadow + interrupt relationship. The first number in each pair is the primary IRQ, + and the second is its shadow IRQ used for VPE#1 control. For example, + <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but + when VPE#1 requests IRQ 8, it will use manipulate the IRQ 3 mask bit. + maxItems: 40 + items: + minimum: 0 + maximum: 40 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupt-parent + - interrupts + +additionalProperties: false + +examples: + - | + intc: interrupt-controller@1fb40000 { + compatible = "econet,en751221-intc"; + reg = <0x1fb40000 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; + }; +...
Document the device tree binding for the interrupt controller in the EcoNet EN751221 MIPS SoC. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> --- If anyone is aware of a standard name for this "shadow interrupt" pattern, please let me know and I will re-send with updated naming. --- .../econet,en751221-intc.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml