From patchwork Thu Oct 17 10:24:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Menzel X-Patchwork-Id: 11195357 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 446B51668 for ; Thu, 17 Oct 2019 10:25:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 228CC2082C for ; Thu, 17 Oct 2019 10:25:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390148AbfJQKZB (ORCPT ); Thu, 17 Oct 2019 06:25:01 -0400 Received: from mx3.molgen.mpg.de ([141.14.17.11]:35973 "EHLO mx1.molgen.mpg.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726248AbfJQKZB (ORCPT ); Thu, 17 Oct 2019 06:25:01 -0400 Received: from rabammel.molgen.mpg.de (rabammel.molgen.mpg.de [141.14.30.220]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmenzel) by mx.molgen.mpg.de (Postfix) with ESMTPSA id BBC19202256BC; Thu, 17 Oct 2019 12:24:57 +0200 (CEST) To: Ralf Baechle , Paul Burton , James Hogan Cc: linux-mips@vger.kernel.org From: Paul Menzel Subject: [PATCH] mips/cavium-octeon: Fix typo *must* in comment Message-ID: <3a1eda2f-bc4b-0958-d609-6376663faa9a@molgen.mpg.de> Date: Thu, 17 Oct 2019 12:24:57 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.0 MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Date: Mon, 2 Sep 2019 11:55:06 +0200 Fixes: 5b3b16880f ("MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.") Signed-off-by: Paul Menzel --- arch/mips/cavium-octeon/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 95034bf5ca83..1f742c32a883 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -844,7 +844,7 @@ void __init prom_init(void) * BIST should always be enabled when doing a soft reset. L2 * Cache locking for instance is not cleared unless BIST is * enabled. Unfortunately due to a chip errata G-200 for - * Cn38XX and CN31XX, BIST msut be disabled on these parts. + * Cn38XX and CN31XX, BIST must be disabled on these parts. */ if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || OCTEON_IS_MODEL(OCTEON_CN31XX))