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[023/120] MIPS: R5900: Add MFSA and MTSA instructions for the special SA register

Message ID 484e5c712f0ff87fcd525b3fc18f1483389844fa.1567326213.git.noring@nocrew.org (mailing list archive)
State RFC
Headers show
Series Linux for the PlayStation 2 | expand

Commit Message

Fredrik Noring Sept. 1, 2019, 3:46 p.m. UTC
The shift amount (SA) register is a 64-bit special register storing the
funnel shift amount. The SA is encoded an implementation-defined manner.
It is therefore not meaningful for software to operate on this value.
Use the MTSAB and MTSAH instructions to set a new funnel shift amount.

The SA is used by the QFSRV (quadword funnel shift right variable)
256-bit multimedia instruction.

MFSA copies the SA register to a 64-bit GPR[1]. The sole purpose of this
instruction is to permit the shift amount to be saved during a context
switch.

MTSA copies a 64-bit GPR rs to the SA register[2]. Note that rs must
contain a value that was originally generated by MFSA. If some other
user-generated value is in rs, the shifting action performed by the
funnel shifter is not defined; that is, MTSA cannot be used to by a
program to set a new funnel shift amount. The sole purpose of this
instruction is to permit the shift amount to be restored during a
context switch. Restrictions:

The three instructions statically preceding a MTSA instruction must
not read or write the SA register; that is, they cannot be either of
the instructions MFSA, QFSRV, or MTSAx.

References:

[1] "TX System RISC TX79 Core Architecture" manual, revision 2.0,
    Toshiba Corporation, p. B-17, https://wiki.qemu.org/File:C790.pdf

[2] Ibid. p. B-20.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
 arch/mips/include/asm/mipsregs.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
diff mbox series

Patch

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index a3b3ee011539..d8c1ffac2824 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2594,6 +2594,28 @@  do {									\
 
 #else
 
+#ifdef CONFIG_CPU_R5900
+#define mfsa()								\
+({									\
+	unsigned long __treg;	/* FIXME: __u64? */			\
+									\
+	__asm__ __volatile__(						\
+	"	mfsa	%0\n"						\
+	: "=r" (__treg));						\
+	__treg;								\
+})
+
+#define mtsa(x)								\
+do {									\
+	unsigned long __treg = (x);/* FIXME: __u64? */			\
+									\
+	__asm__ __volatile__(						\
+	"	mtsa	%0\n"						\
+	:								\
+	: "r" (__treg));						\
+} while (0)
+#endif
+
 #define rddsp(mask)							\
 ({									\
 	unsigned int __res;						\