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[3/6] MIPS: OCTEON: Remove redundant enable of PCIe normal error reporting

Message ID b7eb2cae4f81648a8df5885d5d5f7371a6c436e2.1633369560.git.naveennaidu479@gmail.com (mailing list archive)
State New
Headers show
Series MIPS: OCTEON: Remove redundant AER code | expand

Commit Message

Naveen Naidu Oct. 4, 2021, 5:59 p.m. UTC 
e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS
specific code to enable PCIe and AER error reporting (*irrespective
of CONFIG_PCIEAER value*) because PCI core didn't do that at the time.

Currently when CONFIG_PCIEAER=y, the PCIe normal error reporting is
enabled by pci_enable_pcie_error_reporting() in the aer_probe() path.

It is now no longer necessary for Octeon code to enable PCIe normal
error since it's done when PCIe bus loads the AER service driver.

Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
---
 arch/mips/pci/pci-octeon.c | 7 -------
 1 file changed, 7 deletions(-)
diff mbox series

Patch

diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 8e8b282226cc..2c251018075c 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -114,13 +114,6 @@  int pcibios_plat_dev_init(struct pci_dev *dev)
 		pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
 	}
 
-	/* Enable the PCIe normal error reporting */
-	config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
-	config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
-	config |= PCI_EXP_DEVCTL_FERE;	/* Fatal Error Reporting */
-	config |= PCI_EXP_DEVCTL_URRE;	/* Unsupported Request */
-	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
-
 	/* Find the Advanced Error Reporting capability */
 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 	if (pos) {