[v5,5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers

Commit Message

H. Nikolaus Schaller Oct. 5, 2021, 12:29 p.m. UTC

From: Paul Boddie <[e-mail]>

A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
HDMI support. This requires a new driver, plus device tree and configuration
modifications.

Signed-off-by: Paul Boddie <[e-mail]>
Signed-off-by: H. Nikolaus Schaller <[e-mail]>
---
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 45 ++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

Comments

Paul Cercueil Oct. 5, 2021, 8:50 p.m. UTC | #1

Hi Nikolaus & Paul,

Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller 
<[e-mail]> a écrit :
> From: Paul Boddie <[e-mail]>
> 
> A specialisation of the generic Synopsys HDMI driver is employed for 
> JZ4780
> HDMI support. This requires a new driver, plus device tree and 
> configuration
> modifications.
> 
> Signed-off-by: Paul Boddie <[e-mail]>
> Signed-off-by: H. Nikolaus Schaller <[e-mail]>
> ---
>  arch/mips/boot/dts/ingenic/jz4780.dtsi | 45 
> ++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi 
> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index 9e34f433b9b5..c3c18a59c377 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -424,6 +424,51 @@ i2c4: i2c@10054000 {
>  		status = "disabled";
>  	};
> 
> +	hdmi: hdmi@10180000 {
> +		compatible = "ingenic,jz4780-dw-hdmi";
> +		reg = <0x10180000 0x8000>;
> +		reg-io-width = <4>;
> +
> +		clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
> +		clock-names = "iahb", "isfr";
> +
> +		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
> +		assigned-clock-rates = <27000000>;

Any reason why this is set to 27 MHz? Is it even required? Because with 
the current ci20.dts, it won't be clocked at anything but 48 MHz.

> +
> +		interrupt-parent = <&intc>;
> +		interrupts = <3>;
> +
> +		/* ddc-i2c-bus = <&i2c4>; */
> +
> +		status = "disabled";
> +	};
> +
> +	lcdc0: lcdc0@13050000 {
> +		compatible = "ingenic,jz4780-lcd";
> +		reg = <0x13050000 0x1800>;
> +
> +		clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
> +		clock-names = "lcd", "lcd_pclk";
> +
> +		interrupt-parent = <&intc>;
> +		interrupts = <31>;
> +
> +		status = "disabled";

I think you can keep lcdc0 enabled by default (not lcdc1 though), since 
it is highly likely that you'd want that.

Cheers,
-Paul

> +	};
> +
> +	lcdc1: lcdc1@130a0000 {
> +		compatible = "ingenic,jz4780-lcd";
> +		reg = <0x130a0000 0x1800>;
> +
> +		clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD1PIXCLK>;
> +		clock-names = "lcd", "lcd_pclk";
> +
> +		interrupt-parent = <&intc>;
> +		interrupts = <31>;
> +
> +		status = "disabled";
> +	};
> +
>  	nemc: nemc@13410000 {
>  		compatible = "ingenic,jz4780-nemc", "simple-mfd";
>  		reg = <0x13410000 0x10000>;
> --
> 2.33.0
>

Paul Boddie Oct. 5, 2021, 9:44 p.m. UTC | #2

On Tuesday, 5 October 2021 22:50:12 CEST Paul Cercueil wrote:
> Hi Nikolaus & Paul,
> 
> Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller 
<[e-mail]> a écrit :
> > 
> > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> > b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> > index 9e34f433b9b5..c3c18a59c377 100644
> > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> > @@ -424,6 +424,51 @@ i2c4: i2c@10054000 {
> > 
> >  		status = "disabled";
> >  	
> >  	};
> > 
> > +	hdmi: hdmi@10180000 {
> > +		compatible = "ingenic,jz4780-dw-hdmi";
> > +		reg = <0x10180000 0x8000>;
> > +		reg-io-width = <4>;
> > +
> > +		clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
> > +		clock-names = "iahb", "isfr";
> > +
> > +		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
> > +		assigned-clock-rates = <27000000>;
> 
> Any reason why this is set to 27 MHz? Is it even required? Because with
> the current ci20.dts, it won't be clocked at anything but 48 MHz.

EXCLK will be 48MHz, but the aim is to set the HDMI peripheral clock to 27MHz, 
which is supposedly required. I vaguely recall a conversation about whether we 
were doing this right, but I don't recall any conclusion.

> > +
> > +		interrupt-parent = <&intc>;
> > +		interrupts = <3>;
> > +
> > +		/* ddc-i2c-bus = <&i2c4>; */
> > +
> > +		status = "disabled";
> > +	};
> > +
> > +	lcdc0: lcdc0@13050000 {
> > +		compatible = "ingenic,jz4780-lcd";
> > +		reg = <0x13050000 0x1800>;
> > +
> > +		clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
> > +		clock-names = "lcd", "lcd_pclk";
> > +
> > +		interrupt-parent = <&intc>;
> > +		interrupts = <31>;
> > +
> > +		status = "disabled";
> 
> I think you can keep lcdc0 enabled by default (not lcdc1 though), since
> it is highly likely that you'd want that.

As far as I know, the clock gating for the LCD controllers acts like a series 
circuit, meaning that they both need to be enabled. Some testing seemed to 
confirm this. Indeed, I seem to remember only enabling one clock and not 
getting any output until I figured this weird arrangement out.

Paul

Paul Cercueil Oct. 5, 2021, 9:52 p.m. UTC | #3

Hi Paul,

Le mar., oct. 5 2021 at 23:44:12 +0200, Paul Boddie 
<[e-mail]> a écrit :
> On Tuesday, 5 October 2021 22:50:12 CEST Paul Cercueil wrote:
>>  Hi Nikolaus & Paul,
>> 
>>  Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller
> <[e-mail]> a écrit :
>>  >
>>  > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>  > b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>  > index 9e34f433b9b5..c3c18a59c377 100644
>>  > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>  > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>  > @@ -424,6 +424,51 @@ i2c4: i2c@10054000 {
>>  >
>>  >  		status = "disabled";
>>  >
>>  >  	};
>>  >
>>  > +	hdmi: hdmi@10180000 {
>>  > +		compatible = "ingenic,jz4780-dw-hdmi";
>>  > +		reg = <0x10180000 0x8000>;
>>  > +		reg-io-width = <4>;
>>  > +
>>  > +		clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
>>  > +		clock-names = "iahb", "isfr";
>>  > +
>>  > +		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
>>  > +		assigned-clock-rates = <27000000>;
>> 
>>  Any reason why this is set to 27 MHz? Is it even required? Because 
>> with
>>  the current ci20.dts, it won't be clocked at anything but 48 MHz.
> 
> EXCLK will be 48MHz, but the aim is to set the HDMI peripheral clock 
> to 27MHz,
> which is supposedly required. I vaguely recall a conversation about 
> whether we
> were doing this right, but I don't recall any conclusion.

But right now your HDMI clock is 48 MHz and HDMI works.

>>  > +
>>  > +		interrupt-parent = <&intc>;
>>  > +		interrupts = <3>;
>>  > +
>>  > +		/* ddc-i2c-bus = <&i2c4>; */
>>  > +
>>  > +		status = "disabled";
>>  > +	};
>>  > +
>>  > +	lcdc0: lcdc0@13050000 {
>>  > +		compatible = "ingenic,jz4780-lcd";
>>  > +		reg = <0x13050000 0x1800>;
>>  > +
>>  > +		clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
>>  > +		clock-names = "lcd", "lcd_pclk";
>>  > +
>>  > +		interrupt-parent = <&intc>;
>>  > +		interrupts = <31>;
>>  > +
>>  > +		status = "disabled";
>> 
>>  I think you can keep lcdc0 enabled by default (not lcdc1 though), 
>> since
>>  it is highly likely that you'd want that.
> 
> As far as I know, the clock gating for the LCD controllers acts like 
> a series
> circuit, meaning that they both need to be enabled. Some testing 
> seemed to
> confirm this. Indeed, I seem to remember only enabling one clock and 
> not
> getting any output until I figured this weird arrangement out.

I'm not talking about clocks though, but about LCDC0 and LCDC1.

Cheers,
-Paul

H. Nikolaus Schaller Nov. 7, 2021, 1:45 p.m. UTC | #4

Hi Paul,

> Am 05.10.2021 um 23:52 schrieb Paul Cercueil <[e-mail]>:
> 
> Hi Paul,
> 
> Le mar., oct. 5 2021 at 23:44:12 +0200, Paul Boddie <[e-mail]> a écrit :
>> On Tuesday, 5 October 2021 22:50:12 CEST Paul Cercueil wrote:
>>> Hi Nikolaus & Paul,
>>> Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller
>> <[e-mail]> a écrit :
>>> >
>>> > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> > b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> > index 9e34f433b9b5..c3c18a59c377 100644
>>> > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> > @@ -424,6 +424,51 @@ i2c4: i2c@10054000 {
>>> >
>>> >  		status = "disabled";
>>> >
>>> >  	};
>>> >
>>> > +	hdmi: hdmi@10180000 {
>>> > +		compatible = "ingenic,jz4780-dw-hdmi";
>>> > +		reg = <0x10180000 0x8000>;
>>> > +		reg-io-width = <4>;
>>> > +
>>> > +		clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
>>> > +		clock-names = "iahb", "isfr";
>>> > +
>>> > +		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
>>> > +		assigned-clock-rates = <27000000>;
>>> Any reason why this is set to 27 MHz? Is it even required? Because with
>>> the current ci20.dts, it won't be clocked at anything but 48 MHz.
>> EXCLK will be 48MHz, but the aim is to set the HDMI peripheral clock to 27MHz,
>> which is supposedly required. I vaguely recall a conversation about whether we
>> were doing this right, but I don't recall any conclusion.
> 
> But right now your HDMI clock is 48 MHz and HDMI works.

Is it? How did you find out?

And have you tried to remove assigned-clocks from jz4780.dtsi?

1. I read back:

root@letux:~# cat /sys/kernel/debug/clk/hdmi/clk_rate
26909090
root@letux:~# 

So for me it seems to be running at ~27 MHz.

2. If I remove the assigned-clocks or assigned-clock-rates from DT
the boot process hangs shortly after initializing drm.

3. If I set assigned-clock-rates = <48000000>, HDMI also works.

I get it read back from /sys/kernel/debug/clk/hdmi/clk_rate
of 46736842.

4. Conclusions:
* assigned-clocks are required
* it does not matter if 27 or 48 MHz
* I have no idea which value is more correct
* so I'd stay on the safe side of 27 MHz

5. But despite that found, please look into the programming
manual section 18.1.2.16. There is an

"Import Note: The clock must be between 18M and 27M, it occurs
fatal error if exceeding the range. "

6. Therefore I think it *may* work overclocked with 48MHz
but is not guaranteed or reliable above 27 MHz.

So everything is ok here.

> 
>>> > +
>>> > +		interrupt-parent = <&intc>;
>>> > +		interrupts = <3>;
>>> > +
>>> > +		/* ddc-i2c-bus = <&i2c4>; */
>>> > +
>>> > +		status = "disabled";
>>> > +	};
>>> > +
>>> > +	lcdc0: lcdc0@13050000 {
>>> > +		compatible = "ingenic,jz4780-lcd";
>>> > +		reg = <0x13050000 0x1800>;
>>> > +
>>> > +		clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
>>> > +		clock-names = "lcd", "lcd_pclk";
>>> > +
>>> > +		interrupt-parent = <&intc>;
>>> > +		interrupts = <31>;
>>> > +
>>> > +		status = "disabled";
>>> I think you can keep lcdc0 enabled by default (not lcdc1 though), since
>>> it is highly likely that you'd want that.
>> As far as I know, the clock gating for the LCD controllers acts like a series
>> circuit, meaning that they both need to be enabled. Some testing seemed to
>> confirm this. Indeed, I seem to remember only enabling one clock and not
>> getting any output until I figured this weird arrangement out.
> 
> I'm not talking about clocks though, but about LCDC0 and LCDC1.

Ah, you mean status = "okay"; vs. status = "disabled";

Well, IMHO it is common practise to keep SoC subsystems disabled by
default (to save power and boot time) unless a board specific DTS explicitly
requests the SoC feature to be active. See for example mmc0, mmc1 or i2c0..i2c4.

All these are disabled in jz4780.dtsi and partially enabled in ci20.dts.

Why should lcdc0 be an exception in jz4780.dtsi?

BR and thanks,
Nikolaus

Paul Cercueil Nov. 7, 2021, 7:05 p.m. UTC | #5

Hi,

Le dim., nov. 7 2021 at 14:45:37 +0100, H. Nikolaus Schaller 
<[e-mail]> a écrit :
> Hi Paul,
> 
>>  Am 05.10.2021 um 23:52 schrieb Paul Cercueil <[e-mail]>:
>> 
>>  Hi Paul,
>> 
>>  Le mar., oct. 5 2021 at 23:44:12 +0200, Paul Boddie 
>> <[e-mail]> a écrit :
>>>  On Tuesday, 5 October 2021 22:50:12 CEST Paul Cercueil wrote:
>>>>  Hi Nikolaus & Paul,
>>>>  Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller
>>>  <[e-mail]> a écrit :
>>>>  >
>>>>  > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>  > b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>  > index 9e34f433b9b5..c3c18a59c377 100644
>>>>  > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>  > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>  > @@ -424,6 +424,51 @@ i2c4: i2c@10054000 {
>>>>  >
>>>>  >  		status = "disabled";
>>>>  >
>>>>  >  	};
>>>>  >
>>>>  > +	hdmi: hdmi@10180000 {
>>>>  > +		compatible = "ingenic,jz4780-dw-hdmi";
>>>>  > +		reg = <0x10180000 0x8000>;
>>>>  > +		reg-io-width = <4>;
>>>>  > +
>>>>  > +		clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
>>>>  > +		clock-names = "iahb", "isfr";
>>>>  > +
>>>>  > +		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
>>>>  > +		assigned-clock-rates = <27000000>;
>>>>  Any reason why this is set to 27 MHz? Is it even required? 
>>>> Because with
>>>>  the current ci20.dts, it won't be clocked at anything but 48 MHz.
>>>  EXCLK will be 48MHz, but the aim is to set the HDMI peripheral 
>>> clock to 27MHz,
>>>  which is supposedly required. I vaguely recall a conversation 
>>> about whether we
>>>  were doing this right, but I don't recall any conclusion.
>> 
>>  But right now your HDMI clock is 48 MHz and HDMI works.
> 
> Is it? How did you find out?
> 
> And have you tried to remove assigned-clocks from jz4780.dtsi?
> 
> 1. I read back:
> 
> root@letux:~# cat /sys/kernel/debug/clk/hdmi/clk_rate
> 26909090
> root@letux:~#
> 
> So for me it seems to be running at ~27 MHz.
> 
> 2. If I remove the assigned-clocks or assigned-clock-rates from DT
> the boot process hangs shortly after initializing drm.
> 
> 3. If I set assigned-clock-rates = <48000000>, HDMI also works.
> 
> I get it read back from /sys/kernel/debug/clk/hdmi/clk_rate
> of 46736842.
> 
> 4. Conclusions:
> * assigned-clocks are required
> * it does not matter if 27 or 48 MHz
> * I have no idea which value is more correct
> * so I'd stay on the safe side of 27 MHz
> 
> 5. But despite that found, please look into the programming
> manual section 18.1.2.16. There is an
> 
> "Import Note: The clock must be between 18M and 27M, it occurs
> fatal error if exceeding the range. "

Ok, that's the important information that was missing.

So 27 MHz is OK.

> 6. Therefore I think it *may* work overclocked with 48MHz
> but is not guaranteed or reliable above 27 MHz.
> 
> So everything is ok here.

One thing though - the "assigned-clocks" and "assigned-clock-rates", 
while it works here, should be moved to the CGU node, to respect the 
YAML schemas.

Cheers,
-Paul

> 
>> 
>>>>  > +
>>>>  > +		interrupt-parent = <&intc>;
>>>>  > +		interrupts = <3>;
>>>>  > +
>>>>  > +		/* ddc-i2c-bus = <&i2c4>; */
>>>>  > +
>>>>  > +		status = "disabled";
>>>>  > +	};
>>>>  > +
>>>>  > +	lcdc0: lcdc0@13050000 {
>>>>  > +		compatible = "ingenic,jz4780-lcd";
>>>>  > +		reg = <0x13050000 0x1800>;
>>>>  > +
>>>>  > +		clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
>>>>  > +		clock-names = "lcd", "lcd_pclk";
>>>>  > +
>>>>  > +		interrupt-parent = <&intc>;
>>>>  > +		interrupts = <31>;
>>>>  > +
>>>>  > +		status = "disabled";
>>>>  I think you can keep lcdc0 enabled by default (not lcdc1 though), 
>>>> since
>>>>  it is highly likely that you'd want that.
>>>  As far as I know, the clock gating for the LCD controllers acts 
>>> like a series
>>>  circuit, meaning that they both need to be enabled. Some testing 
>>> seemed to
>>>  confirm this. Indeed, I seem to remember only enabling one clock 
>>> and not
>>>  getting any output until I figured this weird arrangement out.
>> 
>>  I'm not talking about clocks though, but about LCDC0 and LCDC1.
> 
> Ah, you mean status = "okay"; vs. status = "disabled";
> 
> Well, IMHO it is common practise to keep SoC subsystems disabled by
> default (to save power and boot time) unless a board specific DTS 
> explicitly
> requests the SoC feature to be active. See for example mmc0, mmc1 or 
> i2c0..i2c4.
> 
> All these are disabled in jz4780.dtsi and partially enabled in 
> ci20.dts.
> 
> Why should lcdc0 be an exception in jz4780.dtsi?
> 
> BR and thanks,
> Nikolaus
>

H. Nikolaus Schaller Nov. 9, 2021, 8:19 p.m. UTC | #6

Hi Paul,

> Am 07.11.2021 um 20:05 schrieb Paul Cercueil <[e-mail]>:
> 
>> 6. Therefore I think it *may* work overclocked with 48MHz
>> but is not guaranteed or reliable above 27 MHz.
>> So everything is ok here.
> 
> One thing though - the "assigned-clocks" and "assigned-clock-rates", while it works here, should be moved to the CGU node, to respect the YAML schemas.

Trying to do this seems to break boot.

I can boot up to 

[    8.312926] dw-hdmi-ingenic 10180000.hdmi: registered DesignWare HDMI I2C bus driver

and

[   11.366899] [drm] Initialized ingenic-drm 1.1.0 20200716 for 13050000.lcdc0 on minor 0

but then the boot process becomes slow and hangs. Last sign of activity is

[   19.347659] hub 1-0:1.0: USB hub found
[   19.353478] hub 1-0:1.0: 1 port detected
[   32.321760] wlan0_power: disabling

What I did was to just move

		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
		assigned-clock-rates = <27000000>;

from

	hdmi: hdmi@10180000 {

to

	cgu: jz4780-cgu@10000000 {

Does this mean the clock is assigned too early or too late?

Do you have any suggestions since I don't know the details of CGU.

BR and thanks,
Nikolaus

Paul Cercueil Nov. 9, 2021, 8:36 p.m. UTC | #7

Hi Nikolaus,

Le mar., nov. 9 2021 at 21:19:17 +0100, H. Nikolaus Schaller 
<[e-mail]> a écrit :
> Hi Paul,
> 
>>  Am 07.11.2021 um 20:05 schrieb Paul Cercueil <[e-mail]>:
>> 
>>>  6. Therefore I think it *may* work overclocked with 48MHz
>>>  but is not guaranteed or reliable above 27 MHz.
>>>  So everything is ok here.
>> 
>>  One thing though - the "assigned-clocks" and 
>> "assigned-clock-rates", while it works here, should be moved to the 
>> CGU node, to respect the YAML schemas.
> 
> Trying to do this seems to break boot.
> 
> I can boot up to
> 
> [    8.312926] dw-hdmi-ingenic 10180000.hdmi: registered DesignWare 
> HDMI I2C bus driver
> 
> and
> 
> [   11.366899] [drm] Initialized ingenic-drm 1.1.0 20200716 for 
> 13050000.lcdc0 on minor 0
> 
> but then the boot process becomes slow and hangs. Last sign of 
> activity is
> 
> [   19.347659] hub 1-0:1.0: USB hub found
> [   19.353478] hub 1-0:1.0: 1 port detected
> [   32.321760] wlan0_power: disabling
> 
> What I did was to just move
> 
> 		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
> 		assigned-clock-rates = <27000000>;
> 
> from
> 
> 	hdmi: hdmi@10180000 {
> 
> to
> 
> 	cgu: jz4780-cgu@10000000 {
> 
> Does this mean the clock is assigned too early or too late?
> 
> Do you have any suggestions since I don't know the details of CGU.

These properties are already set for the CGU node in ci20.dts:

&cgu {
	/*
	 * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
	 * precision.
	 */
	assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
	assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
	assigned-clock-rates = <48000000>;
};

So you want to update these properties to add the HDMI clock setting, 
like this:

	assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, 
<&cgu JZ4780_CLK_HDMI>;
	assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
	assigned-clock-rates = <48000000>, <0>, <27000000>;

Cheers,
-Paul

H. Nikolaus Schaller Nov. 9, 2021, 8:42 p.m. UTC | #8

> Am 09.11.2021 um 21:36 schrieb Paul Cercueil <[e-mail]>:
> 
> Hi Nikolaus,
> 
> Le mar., nov. 9 2021 at 21:19:17 +0100, H. Nikolaus Schaller <[e-mail]> a écrit :
>> Hi Paul,
>>> Am 07.11.2021 um 20:05 schrieb Paul Cercueil <[e-mail]>:
>>>> 6. Therefore I think it *may* work overclocked with 48MHz
>>>> but is not guaranteed or reliable above 27 MHz.
>>>> So everything is ok here.
>>> One thing though - the "assigned-clocks" and "assigned-clock-rates", while it works here, should be moved to the CGU node, to respect the YAML schemas.
>> Trying to do this seems to break boot.
>> I can boot up to
>> [    8.312926] dw-hdmi-ingenic 10180000.hdmi: registered DesignWare HDMI I2C bus driver
>> and
>> [   11.366899] [drm] Initialized ingenic-drm 1.1.0 20200716 for 13050000.lcdc0 on minor 0
>> but then the boot process becomes slow and hangs. Last sign of activity is
>> [   19.347659] hub 1-0:1.0: USB hub found
>> [   19.353478] hub 1-0:1.0: 1 port detected
>> [   32.321760] wlan0_power: disabling
>> What I did was to just move
>> 		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
>> 		assigned-clock-rates = <27000000>;
>> from
>> 	hdmi: hdmi@10180000 {
>> to
>> 	cgu: jz4780-cgu@10000000 {
>> Does this mean the clock is assigned too early or too late?
>> Do you have any suggestions since I don't know the details of CGU.
> 
> These properties are already set for the CGU node in ci20.dts:

Ah, I didn't look into that. Maybe because I thought adding this should stay in jz4780.dtsi to be available for any board making use of it.

So it gets overwritten and is then completely missing.

> 
> &cgu {
> 	/*
> 	 * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
> 	 * precision.
> 	 */
> 	assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
> 	assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
> 	assigned-clock-rates = <48000000>;
> };
> 
> So you want to update these properties to add the HDMI clock setting, like this:
> 
> 	assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, <&cgu JZ4780_CLK_HDMI>;
> 	assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
> 	assigned-clock-rates = <48000000>, <0>, <27000000>;

Will give it a try.

I would prefer if it could sit in jz4780.dtsi and ci20.dts would just extend it but IMHO this is beyond DTS capabilities.
So we likely have to live with that.

BR and thanks,
Nikolaus

H. Nikolaus Schaller Nov. 9, 2021, 9:14 p.m. UTC | #9

> Am 09.11.2021 um 21:42 schrieb H. Nikolaus Schaller <[e-mail]>:
> 
>> So you want to update these properties to add the HDMI clock setting, like this:
>> 
>> 	assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, <&cgu JZ4780_CLK_HDMI>;
>> 	assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
>> 	assigned-clock-rates = <48000000>, <0>, <27000000>;
> 
> Will give it a try.

Yes, works. So v6 is not far away.

BR,
Nikolaus

Patch

diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 9e34f433b9b5..c3c18a59c377 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -424,6 +424,51 @@  i2c4: i2c@10054000 {
 		status = "disabled";
 	};
 
+	hdmi: hdmi@10180000 {
+		compatible = "ingenic,jz4780-dw-hdmi";
+		reg = <0x10180000 0x8000>;
+		reg-io-width = <4>;
+
+		clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
+		clock-names = "iahb", "isfr";
+
+		assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
+		assigned-clock-rates = <27000000>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <3>;
+
+		/* ddc-i2c-bus = <&i2c4>; */
+
+		status = "disabled";
+	};
+
+	lcdc0: lcdc0@13050000 {
+		compatible = "ingenic,jz4780-lcd";
+		reg = <0x13050000 0x1800>;
+
+		clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
+		clock-names = "lcd", "lcd_pclk";
+
+		interrupt-parent = <&intc>;
+		interrupts = <31>;
+
+		status = "disabled";
+	};
+
+	lcdc1: lcdc1@130a0000 {
+		compatible = "ingenic,jz4780-lcd";
+		reg = <0x130a0000 0x1800>;
+
+		clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD1PIXCLK>;
+		clock-names = "lcd", "lcd_pclk";
+
+		interrupt-parent = <&intc>;
+		interrupts = <31>;
+
+		status = "disabled";
+	};
+
 	nemc: nemc@13410000 {
 		compatible = "ingenic,jz4780-nemc", "simple-mfd";
 		reg = <0x13410000 0x10000>;