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[2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.38 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:39 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 1/7] MIPS: lantiq: Move macro directly to iomem function Date: Sat, 8 Jun 2019 22:48:04 +0200 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek Using the variable as a temporary holder for the macro of the register offset value is not necessary. Move it directly to the IOMEM read/write call. Signed-off-by: Petr Cvek --- arch/mips/lantiq/irq.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 6549499eb202..fb3e1cc2cf6b 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -77,44 +77,42 @@ int ltq_eiu_get_irq(int exin) void ltq_disable_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), + LTQ_ICU_IM0_IER); } void ltq_mask_and_ack_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; - u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); - ltq_icu_w32(im, BIT(offset), isr); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), + LTQ_ICU_IM0_IER); + ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); } static void ltq_ack_irq(struct irq_data *d) { - u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, BIT(offset), isr); + ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); } void ltq_enable_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) | BIT(offset), + LTQ_ICU_IM0_IER); } static int ltq_eiu_settype(struct irq_data *d, unsigned int type)