| Message ID | e7bb27bb8ff03271ee0da7f94fbd41a68bd404ca.1567326213.git.noring@nocrew.org (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | Linux for the PlayStation 2 | expand |
On 9/1/19 5:43 PM, Fredrik Noring wrote: > The following CP0.Config fields are specific to the R5900[1]: > > Field | Bit | Type | Description > ------+-----+------+----------------------------- > DIE | 18 | RW | Enable double issue > ICE | 17 | RW | Enable the instruction cache > DCE | 16 | RW | Enable the data cache > BE | 15 | RO | Enable big-endian > NBE | 13 | RW | Enable nonblocking load > BPE | 12 | RW | Enable branch prediction > ------+-----+------+----------------------------- > > References: > > [1] "TX System RISC TX79 Core Architecture" manual, revision 2.0, > Toshiba Corporation, p. 4-23, https://wiki.qemu.org/File:C790.pdf > > Signed-off-by: Fredrik Noring <noring@nocrew.org> > --- > arch/mips/include/asm/mipsregs.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h > index ec22406c800f..a3b3ee011539 100644 > --- a/arch/mips/include/asm/mipsregs.h > +++ b/arch/mips/include/asm/mipsregs.h > @@ -511,6 +511,14 @@ > #define R5K_CONF_SE (_ULCAST_(1) << 12) > #define R5K_CONF_SS (_ULCAST_(3) << 20) > > +/* Bits specific to the R5900. */ > +#define R5900_CONF_BPE (_ULCAST_(1) << 12) /* Enable branch prediction. */ > +#define R5900_CONF_NBE (_ULCAST_(1) << 13) /* Enable non-blocking load. */ > +#define R5900_CONF_BE (_ULCAST_(1) << 15) /* Enable big-endian (read-only). */ > +#define R5900_CONF_DCE (_ULCAST_(1) << 16) /* Enable the data cache. */ > +#define R5900_CONF_ICE (_ULCAST_(1) << 17) /* Enable the instruction cache. */ > +#define R5900_CONF_DIE (_ULCAST_(1) << 18) /* Enable double issue. */ > + > /* Bits specific to the RM7000. */ > #define RM7K_CONF_SE (_ULCAST_(1) << 3) > #define RM7K_CONF_TE (_ULCAST_(1) << 12) > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index ec22406c800f..a3b3ee011539 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -511,6 +511,14 @@ #define R5K_CONF_SE (_ULCAST_(1) << 12) #define R5K_CONF_SS (_ULCAST_(3) << 20) +/* Bits specific to the R5900. */ +#define R5900_CONF_BPE (_ULCAST_(1) << 12) /* Enable branch prediction. */ +#define R5900_CONF_NBE (_ULCAST_(1) << 13) /* Enable non-blocking load. */ +#define R5900_CONF_BE (_ULCAST_(1) << 15) /* Enable big-endian (read-only). */ +#define R5900_CONF_DCE (_ULCAST_(1) << 16) /* Enable the data cache. */ +#define R5900_CONF_ICE (_ULCAST_(1) << 17) /* Enable the instruction cache. */ +#define R5900_CONF_DIE (_ULCAST_(1) << 18) /* Enable double issue. */ + /* Bits specific to the RM7000. */ #define RM7K_CONF_SE (_ULCAST_(1) << 3) #define RM7K_CONF_TE (_ULCAST_(1) << 12)
The following CP0.Config fields are specific to the R5900[1]: Field | Bit | Type | Description ------+-----+------+----------------------------- DIE | 18 | RW | Enable double issue ICE | 17 | RW | Enable the instruction cache DCE | 16 | RW | Enable the data cache BE | 15 | RO | Enable big-endian NBE | 13 | RW | Enable nonblocking load BPE | 12 | RW | Enable branch prediction ------+-----+------+----------------------------- References: [1] "TX System RISC TX79 Core Architecture" manual, revision 2.0, Toshiba Corporation, p. 4-23, https://wiki.qemu.org/File:C790.pdf Signed-off-by: Fredrik Noring <noring@nocrew.org> --- arch/mips/include/asm/mipsregs.h | 8 ++++++++ 1 file changed, 8 insertions(+)