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Thu, 5 Jul 2018 13:59:04 +0000 From: Ido Schimmel To: idosch@idosch.org Subject: [PATCH net-next mlxsw 4/4] mlxsw: spectrum_router: Optimize processing of VRRP MACs Date: Thu, 5 Jul 2018 16:58:27 +0300 Message-Id: <20180705135827.14770-5-idosch@mellanox.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180705135827.14770-1-idosch@mellanox.com> References: <20180705135827.14770-1-idosch@mellanox.com> MIME-Version: 1.0 X-Originating-IP: [193.47.165.251] X-ClientProxiedBy: DB6P193CA0012.EURP193.PROD.OUTLOOK.COM (2603:10a6:6:29::22) To VI1PR0501MB2334.eurprd05.prod.outlook.com (2603:10a6:800:2c::23) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 008ff399-b4d2-45ab-3df7-08d5e27f780d X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(5600053)(711020)(48565401081)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060)(7193020); SRVR:VI1PR0501MB2334; X-Microsoft-Exchange-Diagnostics: 1; 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Such packets are directed to the router block in the ASIC by an FDB entry that was added in the previous patch. However, in certain cases it is possible to skip this FDB lookup and send such packets directly the router. This is accomplished by adding these special MAC addresses to the RIF cache. If the cache is hit, the packet would skip the L2 lookup and ingress the router with the RIF specified in the cache entry. 1. https://tools.ietf.org/html/rfc5798#section-7.3 Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 12 ++++ .../net/ethernet/mellanox/mlxsw/spectrum_router.c | 73 ++++++++++++++++++++++ 2 files changed, 85 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 1877d9f8a11a..39e25ae177fb 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -4338,6 +4338,18 @@ MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); */ MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); +/* reg_ritr_if_vrrp_id_ipv6 + * VRRP ID for IPv6 + * Access: RW + */ +MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); + +/* reg_ritr_if_vrrp_id_ipv4 + * VRRP ID for IPv4 + * Access: RW + */ +MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); + /* VLAN Interface */ /* reg_ritr_vlan_if_vid diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c index 5f3cec969cca..e2c543568eb5 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c @@ -6443,6 +6443,68 @@ static int mlxsw_sp_inetaddr_vlan_event(struct net_device *vlan_dev, return 0; } +static bool mlxsw_sp_rif_macvlan_is_vrrp4(const u8 *mac) +{ + u8 vrrp4[ETH_ALEN] = { 0x00, 0x00, 0x5e, 0x00, 0x01, 0x00 }; + u8 mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; + + return ether_addr_equal_masked(mac, vrrp4, mask); +} + +static bool mlxsw_sp_rif_macvlan_is_vrrp6(const u8 *mac) +{ + u8 vrrp6[ETH_ALEN] = { 0x00, 0x00, 0x5e, 0x00, 0x02, 0x00 }; + u8 mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; + + return ether_addr_equal_masked(mac, vrrp6, mask); +} + +static int mlxsw_sp_rif_vrrp_add(struct mlxsw_sp *mlxsw_sp, u16 rif_index, + const u8 *mac) +{ + char ritr_pl[MLXSW_REG_RITR_LEN]; + int err; + + if (!mlxsw_sp_rif_macvlan_is_vrrp4(mac) && + !mlxsw_sp_rif_macvlan_is_vrrp6(mac)) + return 0; + + mlxsw_reg_ritr_rif_pack(ritr_pl, rif_index); + err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl); + if (err) + return err; + + if (mlxsw_sp_rif_macvlan_is_vrrp4(mac)) + mlxsw_reg_ritr_if_vrrp_id_ipv4_set(ritr_pl, mac[5]); + else + mlxsw_reg_ritr_if_vrrp_id_ipv6_set(ritr_pl, mac[5]); + + return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl); +} + +static void mlxsw_sp_rif_vrrp_del(struct mlxsw_sp *mlxsw_sp, u16 rif_index, + const u8 *mac) +{ + char ritr_pl[MLXSW_REG_RITR_LEN]; + int err; + + if (!mlxsw_sp_rif_macvlan_is_vrrp4(mac) && + !mlxsw_sp_rif_macvlan_is_vrrp6(mac)) + return; + + mlxsw_reg_ritr_rif_pack(ritr_pl, rif_index); + err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl); + if (err) + return; + + if (mlxsw_sp_rif_macvlan_is_vrrp4(mac)) + mlxsw_reg_ritr_if_vrrp_id_ipv4_set(ritr_pl, 0); + else + mlxsw_reg_ritr_if_vrrp_id_ipv6_set(ritr_pl, 0); + + mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl); +} + static int mlxsw_sp_rif_macvlan_add(struct mlxsw_sp *mlxsw_sp, const struct net_device *macvlan_dev, struct netlink_ext_ack *extack) @@ -6462,6 +6524,11 @@ static int mlxsw_sp_rif_macvlan_add(struct mlxsw_sp *mlxsw_sp, if (err) return err; + err = mlxsw_sp_rif_vrrp_add(mlxsw_sp, rif->rif_index, + macvlan_dev->dev_addr); + if (err) + goto err_rif_vrrp_add; + /* Make sure the bridge driver does not have this MAC pointing at * some other port. */ @@ -6471,6 +6538,11 @@ static int mlxsw_sp_rif_macvlan_add(struct mlxsw_sp *mlxsw_sp, out: return 0; + +err_rif_vrrp_add: + mlxsw_sp_rif_fdb_op(mlxsw_sp, macvlan_dev->dev_addr, + mlxsw_sp_fid_index(rif->fid), false); + return err; } void mlxsw_sp_rif_macvlan_del(struct mlxsw_sp *mlxsw_sp, @@ -6485,6 +6557,7 @@ void mlxsw_sp_rif_macvlan_del(struct mlxsw_sp *mlxsw_sp, */ if (!rif) return; + mlxsw_sp_rif_vrrp_del(mlxsw_sp, rif->rif_index, macvlan_dev->dev_addr); mlxsw_sp_rif_fdb_op(mlxsw_sp, macvlan_dev->dev_addr, mlxsw_sp_fid_index(rif->fid), false); }