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Thu, 18 Jun 2020 08:52:38 -0700 (PDT) Received: from localhost.localdomain ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id 63sm2402267edy.8.2020.06.18.08.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 08:52:38 -0700 (PDT) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org Cc: joro@8bytes.org, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, baolu.lu@linux.intel.com, Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com, zhangfei.gao@linaro.org, xuzaibo@huawei.com, zhengxiang9@huawei.com, fenghua.yu@intel.com, hch@infradead.org, Jean-Philippe Brucker Subject: [PATCH v8 00/12] iommu: Shared Virtual Addressing for SMMUv3 (PT sharing part) Date: Thu, 18 Jun 2020 17:51:13 +0200 Message-Id: <20200618155125.1548969-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Rspamd-Queue-Id: 941EC1814B0C9 X-Spamd-Result: default: False [0.00 / 100.00] X-Rspamd-Server: rspam04 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Since v7 [1], I split the series into three parts to ease review. This first one adds page table sharing to the SMMUv3 driver. The second one adds support for I/O page faults through PRI and Stall, and the last one adds additional and optional features (DVM, VHE and HTTU). SVA needs the three parts to work. No significant change apart from that, I just addressed the previous comments. I'd rather everything went through the IOMMU tree but I'm assuming patch 1 will also go through the x86 tree as part of [2]. It is definitely required by patch 3 which is required by patch 11. I don't know how this kind of conflict is usually resolved, but if it's a problem I could further shrink the series to only patches 4-10 this cycle. [1] https://lore.kernel.org/linux-iommu/20200519175502.2504091-1-jean-philippe@linaro.org/ [2] https://lore.kernel.org/linux-iommu/1592418233-17762-1-git-send-email-fenghua.yu@intel.com/ Fenghua Yu (1): mm: Define pasid in mm Jean-Philippe Brucker (11): iommu/ioasid: Add ioasid references iommu/sva: Add PASID helpers arm64: mm: Pin down ASIDs for sharing mm with devices iommu/io-pgtable-arm: Move some definitions to a header arm64: cpufeature: Export symbol read_sanitised_ftr_reg() iommu/arm-smmu-v3: Share process page tables iommu/arm-smmu-v3: Seize private ASID iommu/arm-smmu-v3: Check for SVA features iommu/arm-smmu-v3: Add SVA device feature iommu/arm-smmu-v3: Implement iommu_sva_bind/unbind() iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops drivers/iommu/Kconfig | 7 + drivers/iommu/Makefile | 1 + arch/arm64/include/asm/mmu.h | 1 + arch/arm64/include/asm/mmu_context.h | 11 +- drivers/iommu/io-pgtable-arm.h | 30 ++ drivers/iommu/iommu-sva-lib.h | 15 + include/linux/ioasid.h | 10 +- include/linux/mm_types.h | 4 + arch/arm64/kernel/cpufeature.c | 1 + arch/arm64/mm/context.c | 95 +++- drivers/iommu/arm-smmu-v3.c | 702 ++++++++++++++++++++++++++- drivers/iommu/intel/iommu.c | 4 +- drivers/iommu/intel/svm.c | 6 +- drivers/iommu/io-pgtable-arm.c | 27 +- drivers/iommu/ioasid.c | 38 +- drivers/iommu/iommu-sva-lib.c | 85 ++++ MAINTAINERS | 3 +- 17 files changed, 977 insertions(+), 63 deletions(-) create mode 100644 drivers/iommu/io-pgtable-arm.h create mode 100644 drivers/iommu/iommu-sva-lib.h create mode 100644 drivers/iommu/iommu-sva-lib.c