From patchwork Tue Oct 1 16:06:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 13818403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9554FCEACE2 for ; Tue, 1 Oct 2024 16:07:04 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id E536E28009B; Tue, 1 Oct 2024 12:07:03 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id E0299280068; Tue, 1 Oct 2024 12:07:03 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id C2E9828009B; Tue, 1 Oct 2024 12:07:03 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id A056C280068 for ; Tue, 1 Oct 2024 12:07:03 -0400 (EDT) Received: from smtpin28.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 4233E1C740C for ; Tue, 1 Oct 2024 16:07:03 +0000 (UTC) X-FDA: 82625512326.28.5A85A81 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) by imf28.hostedemail.com (Postfix) with ESMTP id 28FF4C0024 for ; Tue, 1 Oct 2024 16:06:59 +0000 (UTC) Authentication-Results: imf28.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=JLU2HwTs; dmarc=none; spf=pass (imf28.hostedemail.com: domain of debug@rivosinc.com designates 209.85.216.50 as permitted sender) smtp.mailfrom=debug@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1727798726; a=rsa-sha256; cv=none; b=SSdimxnYHV95Ww6ON0VpJk24Io57tS8A/pbIFj8SmiHyhjXnGmHyOyUflCzdnGKOYSKnYB Dq61AqCC4Zys3vO2Mqju1QykpFSNk+zqEE5H65C74wN5EPLt6yIBZjR1mYeXRNP4ML20yZ 7Tsw8uwbGHdwtR8hlX7/0itQY5iJCPc= ARC-Authentication-Results: i=1; imf28.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=JLU2HwTs; dmarc=none; spf=pass (imf28.hostedemail.com: domain of debug@rivosinc.com designates 209.85.216.50 as permitted sender) smtp.mailfrom=debug@rivosinc.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1727798726; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding:in-reply-to: references:dkim-signature; bh=p/+CAfw719K7trKUOdaKnGov4VX+rClpCqrk7kv+YBo=; b=sA5wMtg211HDAdKGPI/WD1J9cP9NxcIPoGseu9DghtOps3MzNG9xiwohpJNOjrmZppnPks iba2aW9Dl2L7+/7MyHwZooy99N7JmkP6UZWe16yDgkLiIvwUx4BpyniguLen9HgQ3wt/SD g1yzli3QSiIIilb9Nxff95z+g8Xv3C8= Received: by mail-pj1-f50.google.com with SMTP id 98e67ed59e1d1-2e09d9f2021so3822773a91.0 for ; Tue, 01 Oct 2024 09:06:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1727798819; x=1728403619; darn=kvack.org; h=cc:to:content-transfer-encoding:mime-version:message-id:date :subject:from:from:to:cc:subject:date:message-id:reply-to; bh=p/+CAfw719K7trKUOdaKnGov4VX+rClpCqrk7kv+YBo=; b=JLU2HwTsR/eHLEeWGeHPfjAcwU8jWWJIsTXYGVY//llNz3E0OG1g4V0V/4JtjQK3S+ ZhH2Yp4Y748ib7rfsxOsF9YbWs+NZuZgIdfz1tKBd3vpBiS1ue2uGmIx+msc8urnpjwJ b/Y3WRti+GgobJHf8sDLhkExr4TbMeN3CieeuOvrTJBri6LPl5IaGrxkuoOAFmgb+Jm5 JQs7h6Z8el1In/qqEzE/cuIA0AzouhpqAw1PG7nfgztQnLgQDFIoTy+0dvtQmzFtA/OM dtL5vjszqw7kZHTS8X8meveNz+Fy4eamIYhAgnzWqDJP075s8exQU9S0p77SL5Q8PIp1 071Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727798819; x=1728403619; h=cc:to:content-transfer-encoding:mime-version:message-id:date :subject:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=p/+CAfw719K7trKUOdaKnGov4VX+rClpCqrk7kv+YBo=; b=nMCCt8iuIUdh2jJZ++yjimCUw0wHhDkdKHO06mM/zvhhV6BHWbjwnN3NBlP6NQlY9r 8VBzcZIsO1g2y+/fZPiTDG2w+J4vc7PJQNvbYMntwm3h5ybfyCWs29UPHUtdLhO2a1I9 rhTlaQo8K/+d1NNTa0gw9kXi7yPdrbn3gUhnLX/UTkGfh/lOgod1Uls1Q2qxCcV/AqZS Go06WuOzepGLd9zK5APHF+oE22NKYTjUOKkblQWWEWQg1aF8RXDvGzdBH22opTD4eBtS E4q1kkVhpP7rsNF7eCF47vqsU1BFm3JDdzHIuM8khqxI9O7p8tD1rR2Y78vB9+4+jY9i /2wg== X-Forwarded-Encrypted: i=1; AJvYcCVJEjkBMXtfODvsx/fGGGncabp2aRjwy6TFOw7xC/IDSz3bSBJbXxQQfOcyb3HFOxGrbIkYljhtsw==@kvack.org X-Gm-Message-State: AOJu0Yxn8N0rO2MoLpQUCrICKxAHAiPH0J6/Z21JBOwWMCV0LkJi0gcv Ye63PYuUYTOpmKcgy1qnyiTSxiHZuDzI9bGWV96OJxIE7tMwEbBu2upLtAIQujM= X-Google-Smtp-Source: AGHT+IEN2dus5eCDv3FJ6JG+o53WejlfJ1X7DX0j+cv1B0CFXJtJs/0I33VncpmVbaQmMUBwG53XiQ== X-Received: by 2002:a17:90b:46cd:b0:2d3:ba42:775c with SMTP id 98e67ed59e1d1-2e184521a79mr281772a91.1.1727798818585; Tue, 01 Oct 2024 09:06:58 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e06e1d7d47sm13843973a91.28.2024.10.01.09.06.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 09:06:58 -0700 (PDT) From: Deepak Gupta Subject: [PATCH 00/33] riscv control-flow integrity for usermode Date: Tue, 01 Oct 2024 09:06:05 -0700 Message-Id: <20241001-v5_user_cfi_series-v1-0-3ba65b6e550f@rivosinc.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAO0d/GYC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIxMDS2MD3TLT+FKgnvjktMx4iF5d45RkY2OjNIs00yQjJaDGgqLUtMwKsKH RsbW1ALWj2ONkAAAA To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta , David Hildenbrand , Carlos Bilbao , Samuel Holland , Andrew Jones , Conor Dooley , Andy Chiu X-Mailer: b4 0.14.0 X-Rspamd-Queue-Id: 28FF4C0024 X-Rspam-User: X-Rspamd-Server: rspam05 X-Stat-Signature: to4561iwapij4p8h1f1zkzg98zhrtja9 X-HE-Tag: 1727798819-861757 X-HE-Meta: U2FsdGVkX1/g0sAm1Zlohocd29kf6W/E6+dFXkw/f/2txL1+vmTBKIPhUCPgFch6BeH0yJ/NJ4WQxa2YKlr2aBYCy/t3+rbMyh8VcAJG6D9jeNZDxWp8MusZPH/R1f15X6YWBdpEqwdVhGtliVEQrr+YI6/olnib7Om3kWTQm2E7rgzQJuI4a1b3zGYpsWEU61xwVJ6X+ZrFr/kYgFB9gHuDYP7VLNC8fbp4s7wffc5P0RmSppLy7jTKgG6SQiAm59ZLJ6AMKTLAPaMxSHGhXQXNFZqpdTmjR8aKUIpxjwwUAHuPxL7r0Bjqxe5cmviMK/GzP7VXAMK2jgVs7UzXaq1rsyIFEAl7qqaK3FMN56mHQ4dOxUXW2sDk25Vg5LMADmNWNkstfiOR2ooTD+ETpxBGSUmB5V5kUDoJLWTRcH8pB1gIo8+ylNqIaPZtc5lEzqV5MBpWgbEjO3UjOLiA/yfQnJ7Vml1zQkgW0gZL7Hiity7eIJKVTRW/bYrQ+/1Nu17lD0UGV+9xEoSh9piHwUy/AWGvQZ1PKt2ydmoFWtukvgyCm26yvVyrESo/RGin8TTcytcRgpyADNJChMYSiHeqrtoCxc9NRty824b/Dyi3AwbkTN0FgZJkbq9hJtzKvvXBxRgn0UvNjcDOT5P9MvFP9P1+tKSFeisEiIyqK/a0an3wrr8cKnqQ63e/XoULnaUXxLifAc4y5Ink8nQmLHHEnciS9CVbal1ZJlaw6hsaO+Gknxk3F0v0CQ9xxuOqmU9b8q8C3RSYXeZPVfP9EaIc8NHBMWDkB8jF2BISD2iab12RAUbBtP9PsKGosIviHQxrXWI+1YCV+p9Ei6DUdIuRmUyQTHQnfOHGb5eorOqqv9lLm3h3R0W/x47ziRLn1tMQ3EPLGvS/ePHMRFmcNNlIitu2iaFonB0eXCr8vQ1He+Oh+ui7vtjLpaCvKzJEKk6zk9nvKoP5h38dpPc G2I2ZumS o9sjRZUgA+ULLqYfmgeZOtDEmR9LJXFEQxt3B4DbPEB/jotxnEtV5Uoupv8C0wTWM4t6FHJ9vcEMFKcQNdHXAvSKMh335SBEd68PtmEyhuvMRXE9QM1hsW4/y5TiJrt5WUSFzjCH2K8rb85E5rBo5gHAF2xZupvfJjAqVo9mQa/LgrNoQoa9JZb53ZeFzqVV7hx/ldcUhdjCjRIGMtQclJ7h7PckmevKy1M31jbseTTjeAfvmAKzU2X17kZTbaPsYwKL18Y308gEicrn8aZYEPXB43A0FpX6dNZ4J5SX6JbazJPAG28q0rFp4noLtuonEUKU0+I7wSWHSytvH8Dn4xkvzL3ESZHhmRXnBH68xFv0C4O+1Gzpq7RqT2CjFA1QJ77KDUZ95gFUt6zSmT+9mz4Nr+JbAXSEycqivWEC7iDGX7D6VqgA6bIxjH7F4ZInGLCsNfkliUtRz82EcSwsKK4/gHm2iFj60X2n959sNlnNtVnb7rrH5uVqwSM3L6b0pK7mid6sk9VpNookBJW/qjrhnIQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: v5 for cpu assisted riscv user mode control flow integrity. zicfiss and zicfilp [1] are ratified riscv CPU extensions. Changes in this version are - rebased on v6.12-rc1 - Fixed schema related issues in device tree file - Fixed some of the documentation related issues in zicfilp/ss.rst (style issues and added index) - added `SHADOW_STACK_SET_MARKER` so that implementation can define base of shadow stack. - Fixed warnings on definitions added in usercfi.h when CONFIG_RISCV_USER_CFI is not selected. - Adopted context header based signal handling as proposed by Andy Chiu - Added support for enabling kernel mode access to shadow stack using FWFT [4] v4 [3] and v3 [2] are earlier versions of patch series. To get more information on kernel interactions with respect to zicfilp and zicfiss, patch series adds documentation for `zicfilp` and `zicfiss` Documentation/arch/riscv/zicfiss.rst Documentation/arch/riscv/zicfilp.rst How to test this series ======================= Toolchain --------- $ git clone git@github.com:sifive/riscv-gnu-toolchain.git -b cfi-dev $ riscv-gnu-toolchain/configure --prefix= --with-arch=rv64gc_zicfilp_zicfiss --enable-linux --disable-gdb --with-extra-multilib-test="rv64gc_zicfilp_zicfiss-lp64d:-static" $ make -j$(nproc) Qemu ---- $ git clone git@github.com:deepak0414/qemu.git -b zicfilp_zicfiss_ratified_master_july11 $ cd qemu $ mkdir build $ cd build $ ../configure --target-list=riscv64-softmmu $ make -j$(nproc) Opensbi ------- $ git clone git@github.com:deepak0414/opensbi.git -b v6_cfi_spec_split_opensbi $ make CROSS_COMPILE= -j$(nproc) PLATFORM=generic Linux ----- Running defconfig is fine. CFI is enabled by default if the toolchain supports it. $ make ARCH=riscv CROSS_COMPILE=/build/bin/riscv64-unknown-linux-gnu- -j$(nproc) defconfig $ make ARCH=riscv CROSS_COMPILE=/build/bin/riscv64-unknown-linux-gnu- -j$(nproc) Running ------- Modify your qemu command to have: -bios /build/platform/generic/firmware/fw_dynamic.bin -cpu rv64,zicfilp=true,zicfiss=true,zimop=true,zcmop=true vDSO related Opens (in the flux) ================================= I am listing these opens for laying out plan and what to expect in future patch sets. And of course for the sake of discussion. Shadow stack and landing pad enabling in vDSO ---------------------------------------------- vDSO must have shadow stack and landing pad support compiled in for task to have shadow stack and landing pad support. This patch series doesn't enable that (yet). Enabling shadow stack support in vDSO should be straight forward (intend to do that in next versions of patch set). Enabling landing pad support in vDSO requires some collaboration with toolchain folks to follow a single label scheme for all object binaries. This is necessary to ensure that all indirect call-sites are setting correct label and target landing pads are decorated with same label scheme. How many vDSOs --------------- Shadow stack instructions are carved out of zimop (may be operations) and if CPU doesn't implement zimop, they're illegal instructions. Kernel could be running on a CPU which may or may not implement zimop. And thus kernel will have to carry 2 different vDSOs and expose the appropriate one depending on whether CPU implements zimop or not. [1] - https://github.com/riscv/riscv-cfi [2] - https://lore.kernel.org/lkml/20240403234054.2020347-1-debug@rivosinc.com/ [3] - https://lore.kernel.org/all/20240912231650.3740732-1-debug@rivosinc.com/ [4] - https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-firmware-features.adoc --- changelog --------- v4 -- - rebased on 6.11-rc6 - envcfg: Converged with Samuel Holland's patches for envcfg management on per- thread basis. - vma_is_shadow_stack is renamed to is_vma_shadow_stack - picked up Mark Brown's `ARCH_HAS_USER_SHADOW_STACK` patch - signal context: using extended context management to maintain compatibility. - fixed `-Wmissing-prototypes` compiler warnings for prctl functions - Documentation fixes and amending typos. v3 -- envcfg: logic to pick up base envcfg had a bug where `ENVCFG_CBZE` could have been picked on per task basis, even though CPU didn't implement it. Fixed in this series. dt-bindings: As suggested, split into separate commit. fixed the messaging that spec is in public review arch_is_shadow_stack change: arch_is_shadow_stack changed to vma_is_shadow_stack hwprobe: zicfiss / zicfilp if present will get enumerated in hwprobe selftests: As suggested, added object and binary filenames to .gitignore Selftest binary anyways need to be compiled with cfi enabled compiler which will make sure that landing pad and shadow stack are enabled. Thus removed separate enable/disable tests. Cleaned up tests a bit. v2 -- - Using config `CONFIG_RISCV_USER_CFI`, kernel support for riscv control flow integrity for user mode programs can be compiled in the kernel. - Enabling of control flow integrity for user programs is left to user runtime - This patch series introduces arch agnostic `prctls` to enable shadow stack and indirect branch tracking. And implements them on riscv. Signed-off-by: Deepak Gupta --- Andy Chiu (1): riscv: signal: abstract header saving for setup_sigcontext Clément Léger (1): riscv: Add Firmware Feature SBI extensions definitions Deepak Gupta (26): mm: helper `is_shadow_stack_vma` to check shadow stack vma riscv/Kconfig: enable HAVE_EXIT_THREAD for riscv riscv: zicfilp / zicfiss in dt-bindings (extensions.yaml) riscv: zicfiss / zicfilp enumeration riscv: zicfiss / zicfilp extension csr and bit definitions riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE riscv mm: manufacture shadow stack pte riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs riscv mmu: write protect and shadow stack riscv/mm: Implement map_shadow_stack() syscall riscv/shstk: If needed allocate a new shadow stack on clone prctl: arch-agnostic prctl for indirect branch tracking riscv: Implements arch agnostic shadow stack prctls riscv: Implements arch agnostic indirect branch tracking prctls riscv/traps: Introduce software check exception riscv signal: save and restore of shadow stack for signal riscv/kernel: update __show_regs to print shadow stack register riscv/ptrace: riscv cfi status and state via ptrace and in core files riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe riscv: enable kernel access to shadow stack memory via FWFT sbi call riscv: kernel command line option to opt out of user cfi riscv: create a config for shadow stack and landing pad instr support riscv: Documentation for landing pad / indirect branch tracking riscv: Documentation for shadow stack on riscv kselftest/riscv: kselftest for user mode cfi Mark Brown (2): mm: Introduce ARCH_HAS_USER_SHADOW_STACK prctl: arch-agnostic prctl for shadow stack Samuel Holland (3): riscv: Enable cbo.zero only when all harts support Zicboz riscv: Add support for per-thread envcfg CSR values riscv: Call riscv_user_isa_enable() only on the boot hart Documentation/arch/riscv/index.rst | 2 + Documentation/arch/riscv/zicfilp.rst | 115 +++++ Documentation/arch/riscv/zicfiss.rst | 176 +++++++ .../devicetree/bindings/riscv/extensions.yaml | 14 + arch/riscv/Kconfig | 20 + arch/riscv/include/asm/asm-prototypes.h | 1 + arch/riscv/include/asm/cpufeature.h | 15 +- arch/riscv/include/asm/csr.h | 16 + arch/riscv/include/asm/entry-common.h | 2 + arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/asm/mman.h | 24 + arch/riscv/include/asm/pgtable.h | 30 +- arch/riscv/include/asm/processor.h | 2 + arch/riscv/include/asm/sbi.h | 27 ++ arch/riscv/include/asm/switch_to.h | 8 + arch/riscv/include/asm/thread_info.h | 4 + arch/riscv/include/asm/usercfi.h | 89 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/include/uapi/asm/ptrace.h | 22 + arch/riscv/include/uapi/asm/sigcontext.h | 1 + arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/asm-offsets.c | 8 + arch/riscv/kernel/cpufeature.c | 13 +- arch/riscv/kernel/entry.S | 31 +- arch/riscv/kernel/head.S | 12 + arch/riscv/kernel/process.c | 31 +- arch/riscv/kernel/ptrace.c | 83 ++++ arch/riscv/kernel/signal.c | 140 +++++- arch/riscv/kernel/smpboot.c | 2 - arch/riscv/kernel/suspend.c | 4 +- arch/riscv/kernel/sys_hwprobe.c | 2 + arch/riscv/kernel/sys_riscv.c | 10 + arch/riscv/kernel/traps.c | 42 ++ arch/riscv/kernel/usercfi.c | 526 +++++++++++++++++++++ arch/riscv/mm/init.c | 2 +- arch/riscv/mm/pgtable.c | 17 + arch/x86/Kconfig | 1 + fs/proc/task_mmu.c | 2 +- include/linux/cpu.h | 4 + include/linux/mm.h | 5 +- include/uapi/asm-generic/mman.h | 4 + include/uapi/linux/elf.h | 1 + include/uapi/linux/prctl.h | 48 ++ kernel/sys.c | 60 +++ mm/Kconfig | 6 + mm/gup.c | 2 +- mm/mmap.c | 1 + mm/vma.h | 10 +- tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/cfi/.gitignore | 3 + tools/testing/selftests/riscv/cfi/Makefile | 10 + tools/testing/selftests/riscv/cfi/cfi_rv_test.h | 83 ++++ tools/testing/selftests/riscv/cfi/riscv_cfi_test.c | 82 ++++ tools/testing/selftests/riscv/cfi/shadowstack.c | 362 ++++++++++++++ tools/testing/selftests/riscv/cfi/shadowstack.h | 37 ++ 55 files changed, 2178 insertions(+), 42 deletions(-) --- base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc change-id: 20240930-v5_user_cfi_series-3dc332f8f5b2 -- - debug