mbox series

[v15,00/11] AMD broadcast TLB invalidation

Message ID 20250304135816.12356-1-bp@kernel.org (mailing list archive)
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Series AMD broadcast TLB invalidation | expand

Message

Borislav Petkov March 4, 2025, 1:58 p.m. UTC 
From: "Borislav Petkov (AMD)" <bp@alien8.de>

Hi all,

these are Rik's patches from here:

https://lore.kernel.org/r/20250226030129.530345-1-riel@surriel.com

with a bunch of dhansen's and mine edits ontop.

Some stuff is still in-flight but I'm sending the current state because
a bunch of things have changed and we'll need a good base to discuss the
remaining changes pending.
 
Preliminary build and boot tests look good but that doesn't say a whole lot.

Thx.

Rik van Riel (11):
  x86/mm: Consolidate full flush threshold decision
  x86/mm: Add INVLPGB feature and Kconfig entry
  x86/mm: Add INVLPGB support code
  x86/mm: Use INVLPGB for kernel TLB flushes
  x86/mm: Use broadcast TLB flushing in page reclaim
  x86/mm: Add global ASID allocation helper functions
  x86/mm: Handle global ASID context switch and TLB flush
  x86/mm: Add global ASID process exit helpers
  x86/mm: Enable broadcast TLB invalidation for multi-threaded processes
  x86/mm: Do targeted broadcast flushing from tlbbatch code
  x86/mm: Enable AMD translation cache extensions

 arch/x86/Kconfig.cpu                     |   4 +
 arch/x86/include/asm/cpufeatures.h       |   1 +
 arch/x86/include/asm/disabled-features.h |   8 +-
 arch/x86/include/asm/mmu.h               |  12 +
 arch/x86/include/asm/mmu_context.h       |  10 +-
 arch/x86/include/asm/msr-index.h         |   2 +
 arch/x86/include/asm/tlb.h               | 126 ++++++
 arch/x86/include/asm/tlbflush.h          |  96 ++++-
 arch/x86/kernel/cpu/amd.c                |  10 +
 arch/x86/mm/tlb.c                        | 506 +++++++++++++++++++++--
 tools/arch/x86/include/asm/msr-index.h   |   2 +
 11 files changed, 730 insertions(+), 47 deletions(-)