Message ID | 167601998765.1924368.258370414771847699.stgit@dwillia2-xfh.jf.intel.com (mailing list archive) |
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State | New |
Headers | show
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X-IronPort-AV: E=McAfee;i="6500,9779,10616"; a="329003075" X-IronPort-AV: E=Sophos;i="5.97,286,1669104000"; d="scan'208";a="329003075" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2023 01:06:28 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10616"; a="913463849" X-IronPort-AV: E=Sophos;i="5.97,286,1669104000"; d="scan'208";a="913463849" Received: from hrchavan-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.209.46.42]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2023 01:06:28 -0800 Subject: [PATCH v2 11/20] cxl/region: Enable CONFIG_CXL_REGION to be toggled From: Dan Williams <dan.j.williams@intel.com> To: linux-cxl@vger.kernel.org Cc: Vishal Verma <vishal.l.verma@intel.com>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Dave Jiang <dave.jiang@intel.com>, Gregory Price <gregory.price@memverge.com>, Fan Ni <fan.ni@samsung.com>, dave.hansen@linux.intel.com, linux-mm@kvack.org, linux-acpi@vger.kernel.org Date: Fri, 10 Feb 2023 01:06:27 -0800 Message-ID: <167601998765.1924368.258370414771847699.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <167601992097.1924368.18291887895351917895.stgit@dwillia2-xfh.jf.intel.com> References: <167601992097.1924368.18291887895351917895.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Content-Type: text/plain; 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CXL RAM and the 'Soft Reserved' => 'System RAM' default
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diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 0ac53c422c31..163c094e67ae 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -104,12 +104,22 @@ config CXL_SUSPEND depends on SUSPEND && CXL_MEM config CXL_REGION - bool + bool "CXL: Region Support" default CXL_BUS # For MAX_PHYSMEM_BITS depends on SPARSEMEM select MEMREGION select GET_FREE_REGION + help + Enable the CXL core to enumerate and provision CXL regions. A CXL + region is defined by one or more CXL expanders that decode a given + system-physical address range. For CXL regions established by + platform-firmware this option enables memory error handling to + identify the devices participating in a given interleaved memory + range. Otherwise, platform-firmware managed CXL is enabled by being + placed in the system address map and does not need a driver. + + If unsure say 'y' config CXL_REGION_INVALIDATION_TEST bool "CXL: Region Cache Management Bypass (TEST)"