From patchwork Thu Oct 11 15:16:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-cheng Yu X-Patchwork-Id: 10636907 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A939B17E1 for ; Thu, 11 Oct 2018 15:22:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 96C8B2BA40 for ; Thu, 11 Oct 2018 15:22:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 94BB02BA2C; Thu, 11 Oct 2018 15:22:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF5752BA4C for ; Thu, 11 Oct 2018 15:22:44 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 0814D6B029B; Thu, 11 Oct 2018 11:21:46 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 014426B029D; Thu, 11 Oct 2018 11:21:45 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id D9D596B029E; Thu, 11 Oct 2018 11:21:45 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by kanga.kvack.org (Postfix) with ESMTP id 91E036B029B for ; Thu, 11 Oct 2018 11:21:45 -0400 (EDT) Received: by mail-pf1-f200.google.com with SMTP id 14-v6so8050595pfk.22 for ; Thu, 11 Oct 2018 08:21:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-original-authentication-results:x-gm-message-state:from:to:cc :subject:date:message-id:in-reply-to:references; bh=/yofMfJkctWwkJZBDJxtB9MQCUIfJdSPsgtfuOwxmtQ=; b=PeRaywTpF/QroHAqs1eMKCnye4RGlsSJNXZsasxKL4bv7cGdnBSHBLOXmJTHuk6jnI F5rPXOl/2vopVa/1WJ+xSxfgI9ahUPDeXA4LcYVMSUeRR9fQ0UUaTstMKoLD1rfl9pXd ypQLOtwJVPhsT+kg2ikWSbD5xCoB2z/LkzG5kLsXKjqiUqtD2yd3Xxc2h1xWR2eqHw96 UCyC35EMbQ4GAIUDINj+lnl6FA5nlnSI7athfjrLSbOQlXg7eVmoAcUNqEasiVf8MkVf IIiBZJnBNEppN9EPfKjXgGafyA31+nIfsV3LsBjZnKsF3FXFArMRsLy4JdLe5zfl7YcB 2cNw== X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of yu-cheng.yu@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=yu-cheng.yu@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Gm-Message-State: ABuFfohDOwKDa+ETRkw0P99QcFly/03x8R3RMnBye9jgeNHAZGgLtMih iWr7wGmsCWdiclFod1xl7V8+MBCp5FcQKkez4RdEHghc7wDp5ZmFm2XFOnhr83xjkaBz++ZgOys HWha2jyKuPtH0OWrAmkDmOZWxJrkNpi14VOXh1o5GzfH7tDaG+WAemU9SmZmmokAguQ== X-Received: by 2002:a63:cb51:: with SMTP id m17-v6mr1765257pgi.105.1539271305267; Thu, 11 Oct 2018 08:21:45 -0700 (PDT) X-Google-Smtp-Source: ACcGV61RIagAzPnHvl0ToS3FeL/4ArAYsm6n/2QXIepw7HQFQxwwVne0PK2S4hO5E3En8YE/SZ8m X-Received: by 2002:a63:cb51:: with SMTP id m17-v6mr1765205pgi.105.1539271304406; Thu, 11 Oct 2018 08:21:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539271304; cv=none; d=google.com; s=arc-20160816; b=Q6L+Lxi8fQutbcsMClD1Ob7jj4X0z1BdSXr9mV6oP4PNRmXbxCNAiNzY2f3YC4irSu 8CiGzjSmRa+wzoQQ23MrfYJBWOM4f+lN6PPndMqyRoDylUrkijB4D+XJkNqblT/sN3iP mcHprMbh1wNIfgtCaXlerTnlfhfnaq3t8E+09S29dicmVF9cRVceFFegNaQV1I1zO/p/ zNi1lFef82WsBhh0Pj+QBrfSDT3aZZMr227bxLLUP/otTifu11iTQvO3BkCYAw/yUTg5 Z204td6IN4IrSpQj8YH7PqxY33JpBurOEqre9fBAKzDMdOM608dHS6ZDlne2YcWVHLdg Ofhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from; bh=/yofMfJkctWwkJZBDJxtB9MQCUIfJdSPsgtfuOwxmtQ=; b=ir2iyzu8pWOOJ2UEGvMCVfHoXrhNN/8JTsNZDqyX/aXq94eLaWqhmVe/I++BB/qVDm 0Q7RmJMbTR48KSYeBnLIetnrnZilXEEhXYQ8Jxv5SHb6+N3xHOFsam13xLqp1d0aAITK FlD8cS7TtVkyWFl4Sa6AaU42nhj3QEz2nlLpYlvFp0NLCsFJgmozQa0vPHBg0Z/FK4Q9 bmHSSamxucm7eFB/xcDWGpeK4zM6gAa9kwufulpBo80u6UOhVTjt0T496EvLvTlj7g2d J+SgoVFsfYngtfvAPCJW4DkuywXdU8uo3y7bSi/qF5sdPtADjYQZc/mFFbXxehqfK6CR ZTug== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of yu-cheng.yu@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=yu-cheng.yu@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from mga09.intel.com (mga09.intel.com. [134.134.136.24]) by mx.google.com with ESMTPS id w90-v6si28024425pfk.208.2018.10.11.08.21.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Oct 2018 08:21:44 -0700 (PDT) Received-SPF: pass (google.com: domain of yu-cheng.yu@intel.com designates 134.134.136.24 as permitted sender) client-ip=134.134.136.24; Authentication-Results: mx.google.com; spf=pass (google.com: domain of yu-cheng.yu@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=yu-cheng.yu@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2018 08:21:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,368,1534834800"; d="scan'208";a="77271620" Received: from 2b52.sc.intel.com ([143.183.136.147]) by fmsmga007.fm.intel.com with ESMTP; 11 Oct 2018 08:21:43 -0700 From: Yu-cheng Yu To: x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue Cc: Yu-cheng Yu Subject: [PATCH v5 02/11] x86/cet/ibt: User-mode indirect branch tracking support Date: Thu, 11 Oct 2018 08:16:45 -0700 Message-Id: <20181011151654.27221-3-yu-cheng.yu@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011151654.27221-1-yu-cheng.yu@intel.com> References: <20181011151654.27221-1-yu-cheng.yu@intel.com> X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP Add user-mode indirect branch tracking enabling/disabling and supporting routines. Signed-off-by: H.J. Lu Signed-off-by: Yu-cheng Yu --- arch/x86/include/asm/cet.h | 8 ++++++ arch/x86/include/asm/disabled-features.h | 8 +++++- arch/x86/kernel/cet.c | 31 ++++++++++++++++++++++++ arch/x86/kernel/cpu/common.c | 17 +++++++++++++ arch/x86/kernel/process.c | 1 + 5 files changed, 64 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cet.h b/arch/x86/include/asm/cet.h index 6fa23a41580c..082abf5e8528 100644 --- a/arch/x86/include/asm/cet.h +++ b/arch/x86/include/asm/cet.h @@ -12,8 +12,11 @@ struct task_struct; struct cet_status { unsigned long shstk_base; unsigned long shstk_size; + unsigned long ibt_bitmap_addr; + unsigned long ibt_bitmap_size; unsigned int locked:1; unsigned int shstk_enabled:1; + unsigned int ibt_enabled:1; }; #ifdef CONFIG_X86_INTEL_CET @@ -25,6 +28,9 @@ void cet_disable_shstk(void); void cet_disable_free_shstk(struct task_struct *p); int cet_restore_signal(unsigned long ssp); int cet_setup_signal(bool ia32, unsigned long rstor, unsigned long *new_ssp); +int cet_setup_ibt(void); +int cet_setup_ibt_bitmap(void); +void cet_disable_ibt(void); #else static inline int prctl_cet(int option, unsigned long arg2) { return -EINVAL; } static inline int cet_setup_shstk(void) { return -EINVAL; } @@ -35,6 +41,8 @@ static inline void cet_disable_free_shstk(struct task_struct *p) {} static inline int cet_restore_signal(unsigned long ssp) { return -EINVAL; } static inline int cet_setup_signal(bool ia32, unsigned long rstor, unsigned long *new_ssp) { return -EINVAL; } +static inline int cet_setup_ibt(void) { return -EINVAL; } +static inline void cet_disable_ibt(void) {} #endif #define cpu_x86_cet_enabled() \ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 3624a11e5ba6..ce5bdaf0f1ff 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -62,6 +62,12 @@ #define DISABLE_SHSTK (1<<(X86_FEATURE_SHSTK & 31)) #endif +#ifdef CONFIG_X86_INTEL_BRANCH_TRACKING_USER +#define DISABLE_IBT 0 +#else +#define DISABLE_IBT (1<<(X86_FEATURE_IBT & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -72,7 +78,7 @@ #define DISABLED_MASK4 (DISABLE_PCID) #define DISABLED_MASK5 0 #define DISABLED_MASK6 0 -#define DISABLED_MASK7 (DISABLE_PTI) +#define DISABLED_MASK7 (DISABLE_PTI|DISABLE_IBT) #define DISABLED_MASK8 0 #define DISABLED_MASK9 (DISABLE_MPX) #define DISABLED_MASK10 0 diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c index 17ad328586aa..40c4c08e5e31 100644 --- a/arch/x86/kernel/cet.c +++ b/arch/x86/kernel/cet.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -296,3 +298,32 @@ int cet_setup_signal(bool ia32, unsigned long rstor_addr, set_shstk_ptr(ssp); return 0; } + +int cet_setup_ibt(void) +{ + u64 r; + + if (!cpu_feature_enabled(X86_FEATURE_IBT)) + return -EOPNOTSUPP; + + rdmsrl(MSR_IA32_U_CET, r); + r |= (MSR_IA32_CET_ENDBR_EN | MSR_IA32_CET_NO_TRACK_EN); + wrmsrl(MSR_IA32_U_CET, r); + + current->thread.cet.ibt_enabled = 1; + return 0; +} + +void cet_disable_ibt(void) +{ + u64 r; + + if (!cpu_feature_enabled(X86_FEATURE_IBT)) + return; + + rdmsrl(MSR_IA32_U_CET, r); + r &= ~(MSR_IA32_CET_ENDBR_EN | MSR_IA32_CET_LEG_IW_EN | + MSR_IA32_CET_NO_TRACK_EN); + wrmsrl(MSR_IA32_U_CET, r); + current->thread.cet.ibt_enabled = 0; +} diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index c3960326b67f..785e387cfdfd 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -435,6 +435,23 @@ static __init int setup_disable_shstk(char *s) __setup("no_cet_shstk", setup_disable_shstk); #endif +#ifdef CONFIG_X86_INTEL_BRANCH_TRACKING_USER +static __init int setup_disable_ibt(char *s) +{ + /* require an exact match without trailing characters */ + if (s[0] != '\0') + return 0; + + if (!boot_cpu_has(X86_FEATURE_IBT)) + return 1; + + setup_clear_cpu_cap(X86_FEATURE_IBT); + pr_info("x86: 'no_cet_ibt' specified, disabling Branch Tracking\n"); + return 1; +} +__setup("no_cet_ibt", setup_disable_ibt); +#endif + /* * Some CPU features depend on higher CPUID levels, which may not always * be available due to CPUID level capping or broken virtualization diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index f240fce2b20f..f44c26bf6d28 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -137,6 +137,7 @@ void flush_thread(void) memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); cet_disable_shstk(); + cet_disable_ibt(); fpu__clear(&tsk->thread.fpu); }